Date

December 21st-23rd, 2015

Location

Indore, India

Attendees

-

Speakers

TBA

About iNIS/ The IEEE International Symposium on Nanoelectronic and Information Systems

Efficient and secure data sensing, storage and processing play pivotal roles in the current information age. State-of-the-art nanoelectronic technology based very-large-scale-integration (VLSI) systems caters to the needs of efficient sensing, storage, and computing. At the same time, efficient algorithms and software used for faster analysis and retrieval of desired information are becoming increasingly important. Big data which are large, complex data sets, are now a part of the Internet world. Storing and processing needs of the enormous amount of structured and unstructured data are getting increased challenging. At the same time, Internet of Things (IoT) and cyber-physical systems (CPS) have been evolving with the simultaneous development of hardware and software. The performance and efficiency of the present as well as the future generation of computing and information processing systems are largely dependent upon advances in both hardware and software. The primary objective of iNIS is aimed to provide a platform for both hardware and software researchers to interact under one umbrella for further development of efficient and secure information processing circuits and systems.

iNIS 2015 is sponsored by IEEE Computer Society (IEEE-CS) under the technical committee on VLSI (TCVLSI) and technically co-sponsorship by IEEE Circuits and Systems Society (IEEE-CAS) as well as IEEE Council on EDA (IEEE-CEDA).

Call For Papers / All the Details

Call for Papers

Technical Scope Deadlines Submit A Paper

Technical Scope / 6 Tracks

Nanoelectronic VLSI and Sensor Systems (NVS)

Posted on 22nd Feb 2015

Different revolutionary and evolutionary technologies in nanoscale have evolved to cater to the needs of future generation computing and information processing systems. Some of the thrust areas in this domain include:

  • a) Nanotechnologies, nanowire, nanotubes and nano-sensors;
  • b) Molecular electronics, bio-sensors and biologically-inspired computing;
  • c) Nanoelectronics for energy harvesting;
  • d) Spintronics, domain-wall, and phase-change memories;
  • e) Memristor and memristive systems;
  • f) Advanced 3D ICs & 3D packaging;
  • g) On-chip interconnection network design, modeling, and simulation;
  • h) GPU, HPC and large-scale cloud-based computing;
  • i) Quantum computing;
  • j) Application specific circuit, system, and sensor design using nanoelectronics; and
  • k) computer-aided design (CAD) methods covering these areas.

Energy-Efficient, Reliable VLSI Systems (ERS)

Posted on 22nd Feb 2015

Consumption of energy or power dissipation has become a major issue in today’s nanoelectronic and information processing systems. Researchers are trying to address and overcome this critical bottleneck in different ways. Some of the major thrust are as follows:

  • a) Energy efficient hardware-software design and co-synthesis;
  • b) Energy efficient applications using field-programmable gate arrays (FPGAs);
  • c) Sustainability of energy efficient applications;
  • d) Dynamic power management;
  • e) Modelling, simulation and validation;
  • f) Energy generation, recovery and management systems;
  • g) Reliability analysis, modeling, and reliable system design;
  • h) Low-power wearable and implantable systems;
  • i) multi-core systems, network-on-chip and MPSoCs; and
  • j) computer-aided design (CAD) methods covering these areas.

Hardware/Software Solutions for Big Data (SBD)

Posted on 22nd Feb 2015

The large, complex data set that are difficult to process using traditional data processing tools are called big data which provide multiple challenges including privacy, analysis, search, storage, transfer, and visualization. Novel hardware and software mechanism are needed to addresses the challenges for the big data to make it useful for the end users of big data. The issues in discussion include performance evaluation, optimizations, accessibility and usability of new technologies. Topics of interests include, but are not limited to the followings:

  • a) Big Data – regression, machine learning, and exploitation;
  • b) Graphs and networks for big data;
  • c) Distributed, and scalable systems for big data;
  • d) Application specific systems using big data;
  • e) Privacy, integrity, and security in big data;
  • f) Storage solutions for big data;
  • g) Search and mining techniques in big data; and
  • h) Hardware designs for big data.

Hardware/Software for Internet of Things (IOT)

Posted on 22nd Feb 2015

IoT envisions the development of tools, techniques, and standards to make ‘things’ more intelligent and programmable to develop more capable ‘things’ to address the necessity of human beings. It covers all types of sensors, communication protocols, computational tools, techniques, devices, processors, embedded systems, data warehousing, big data, cloud computing, server farms, grid computing etc. Topics of interests include the following:

  • a) IoT architecture;
  • b) IoT enabling technologies, services and applications;
  • c) IoT system integration, management, and standards;
  • d) IoT big data analytics;
  • e) IoT security and privacy concerns;
  • f) IoT at nanoscale; and
  • g) Emerging hardware/software solutions for IoT.

Hardware for Secure Information Processing (SIP)

Posted on 22nd Feb 2015

Due to ever increasing demand of network and information contents, hardware capacity for storage, analytics, and processing are catching the eyes of researchers to provide efficient solution to the above. Some of the thrust areas are as follows:

  • a) Circuits and systems for digital rights management (DRM), watermarking, and encryption;
  • b) Data protection strategies and controls;
  • c) Mobile security and bring your own device (BYOD);
  • d) Medical device security;
  • e) Cyber security; and
  • f) Emerging embedded solutions for security.

Cyber Physical Systems and Social Networks (CSN)

Posted on 22nd Feb 2015

CPS provides the efficient integration of computation, networking, and physical processes to cater the needs of next generation embedded computing and information processing. Social networks are playing a dominant role in business intelligence and analytics nowadays. Special types of hardware and software are being developed to handle the enormous amount of unstructured data available via such networks. Some of the thrust areas are as follows:

  • a) Modeling of distributed real-time software for CPS;
  • b) Mobile cyber-physical systems;
  • c) Design challenges of CPS;
  • d) Data portability and management;
  • e) Graphs, algorithms, and Disambiguation in semantic search; and
  • f) Special purpose architectural solution.

Important Information / Check back often for updates

Student Travel Grants and Awards

We are pleased to announce Student Travel Grants and Best Paper award at iNIS 2015:

  • TCVLSI Best Paper Award (1) - $100
  • Student Travel (4 grants) - $200 each, under IEEE-CAS outreach initiative.

Submission Deadline

Due On 20th July 2015 (Extended to: 31st July 2015)

The Symposium program will include contributed papers and speakers invited by the committee. Authors should submit their original work.
Initial submissions to iNIS-2015 are limited to 6 pages.
The manuscripts need to be formatted as a IEEE-CS double column conference format using the templates located here .
Manuscripts in PDF format (without author information for double-blind review) should be submitted using the following link.

Submit Your Paper Here

Final Paper Version

Due On 5th October 2015

iNIS-2015 will have a publish a proceedings through IEEE-CS conference publication services (CPS). Selected papers from iNIS 2015 will be invited for submission to a journal special issue. The double-blind review selection process is based on reviewer feedback and quality of conference presentation.




Call For Special Sessions and Panels

iNIS 2015 will consider proposals for special sessions as well as panels. Special session and panel proposals can be submitted to the special session chairs by email: xinli@cmu.edu and siva.yellampalli@utltraining.com. The submission deadline is the same as specified for the regular paper submissions.




Call For Student Research Symposium Papers

iNIS 2015 will host a student research forum. A single 2-page pdf file formatted using IEEE-CS conference format for student research forum paper can be submitted to the student forum chairs by email: asengupt@iiti.ac.in and bishnu.iisc@gmail.com. All the accepted student research forum papers will be published in the conference souvenir. A selected top 10 of these will be published in the iNIS-2015 proceedings.

Call for Student Research Forum Papers

Register now / early bird pricing until Nov 16!

Registration Details





iNIS 2015 Keynote Speakers

Dr. Dharma P. Agrawal
Ohio Board of Regents Distinguished Professor and
Director, Center for Distributed and Mobile Computing, EECS Department
Tel: 513-556-4756, Email: dpa@cs.uc.edu, Website: www.cs.uc.edu/~dpa
University of Cincinnati, Cincinnati, OH 452221-0030.


Abstract
Wireless Sensor Networks (WSNs) were primarily introduced for defense application, with an objective of monitoring enemy’s activities without any human intervention. In recent years, introduction of IoT has added another dimension to volume of data. In this talk, we consider two complimentary scheme of handling data for instantaneous sensing and 24x7 transmitting important physiological signals. The first step consists of transmitting biomedical data at needed rate without affecting accuracy of results. The second step involves aggregation of data over period of time. Pulmonary Artery Pressure (PAP) and Electrocardiogram (ECG/EKG) are selected as two preliminary physiological signals for Cardio-Vascular Diseases (CVDs). We use a Wireless Body Area Sensor Network (WBASN) to get the physiological data from a user's body and transmit them to a WBAN coordinator. The second step is to aggregate sensor data by combining overtime as signals change slowly over time. Effectiveness of such an aggregation scheme is illustrated by measuring the degree of compression for EEG scalp readings, gait measurement in patients with neurodegenerative conditions, and motor movement signals in normal subjects. Final comments are added to provide glimpse of what can be done to handle volume of biomedical data in the context of IoT.

Short Biography of Dr. Dharma P. Agrawal

Dharma P. Agrawal is the Ohio Board of Regents Distinguished Professor and the founding director for the Center for Distributed and Mobile Computing in the Department of Electrical Engineering and Computing Systems. He has been a faculty member at the ECE Dept., Carnegie Mellon University (on sabbatical leave), N.C. State University, Raleigh and the Wayne State University. His current research interests include applications of sensor networks in monitoring Parkinson’s disease patients and neurosis, applications of sensor networks in monitoring fitness of athletes’ personnel wellness, applications of sensor networks in monitoring firefighters physical condition in Computers, the Journal of Parallel and Distributed Systems and the International Journal of High Speed Computing. He has been the Program Chair and General Chair for numerous international conferences and meetings. He has received numerous certificates from the IEEE Computer Society. He was awarded a Third Millennium Medal, by the IEEE for his outstanding contributions. He has delivered keynote speech at 38 different international conferences. He has published over 666 papers, given 57 different tutorials and extensive training courses in various conferences in USA, and numerous institutions in Taiwan, Korea, Jordan, UAE, Malaysia, and India in the areas of Ad hoc and Sensor Networks and Mesh Networks, including security issues. He has graduated 70 PhDs and 58 MS students. He has been named as an ISI Highly Cited Researcher, is a Fellow of the IEEE, the ACM, the AAAS and the World Innovation Foundation, and a recent recipient of 2008 IEEE CS Harry Goode Award. Recently, in June 2011, he was selected as the best Mentor for Doctoral Students at the University of Cincinnati. Recently, he has been inducted as a charter fellow of the National Academy of Inventors. He has also been elected a Fellow of the IACSIT (International Association of Computer Science and Information Technology), 2013.

Dr. Michel Renovell
Deputy Director of Robotics and Microelectronics of Montpellier (LIRMM), France
Tel: +33 467 418 523, E-mail: renovell@lirmm.fr
LIRMM – University of Montpellier, 161 rue Ada 34095 Montpellier France


Abstract
With today manufacturing technology, it is not possible to eliminate all defects and ensure every manufactured unit is perfect. Instead, each manufactured unit must be tested so that defective parts are not shipped to a customer. Different Test Strategies are commonly used since none is considered as optimal in terms of low defect level. Most companies use some but not all of the following three Test Strategies: the Static Voltage strategy, the Dynamic Voltage or Delay strategy, the Static or Dynamic Current (IDDX) strategy.
While using different approaches, these different test strategies have a common objective: reveal the presence in the chip of defects or deviations that may create a dysfunction. Knowing the complexity of today defects, it is admitted that the classical fault models used for test generation cannot guarantee a satisfactory detection of defects. This implies that new test generation technique specifically oriented to defects have to be defined. So, we must analyze and understand the electrical behavior of the defect and describe its behavior through an adequate ‘defect model’. Then, defect simulation techniques and defect-oriented ATPG techniques must be proposed to allow specific test generation for these defects.
This presentation focuses on spot defects that manifest themselves as shorts or opens in the interconnect or in the MOS transistors: ‘Interconnect open’, ‘Interconnect short’, ‘Floating gate’, and ‘Gate-Oxide-Short’ are analyzed in detail using different model levels. For every defect, it is shown that the electrical behavior is in fact not predictable due to the presence of random parameters. In order to tackle the problem of unpredictability, unified concepts are proposed that allow new test generation techniques guaranteeing coverage of unpredictable defects.

Short Biography of Dr. Michel Renovell

Michel Renovell joined in 1986 the Laboratory of Computer Science, Robotics and Microelectronics of Montpellier (LIRMM) where he was a researcher funded by the French National Council for Scientific Research (CNRS). From 1995 to 2005, he served as head of the Microelectronics team and he is now Deputy-Director of LIRMM (420 staff members). Since 2006, he also serves as Assistant-Director for the CNRS National Institute for Information Sciences (INS2I) managing more than 60 labs in France. He is a member of the editorial board of JETTA and the VLSI Journal. Michel was member of the editorial board of IEEE Design & Test general and he was chair or program chair of many conferences (ETS, VTS, DELTA, IMSTW, FPL, SBCCI, DDECS...), he has published over 240 international papers and has received several best paper awards. In 2013 he has been nominated ‘IEEE Fellow’ for his contribution to ‘Defect Modelling’. His research interests include: Defect modelling, Analog testing and FPGA testing.

Dr. Mircea Stan
Professor in the Charles L. Brown Department of Electrical and Computer Engineering
Director of the HPLP Lab, co-Director of the Center for Automata Processing
Tel: (434) 924 3503, E-mail: mircea@virginia.edu, Website: http://www.ee.virginia.edu/~mrs8n/
University of Virginia, Charlottesville, VA 22904, USA


Abstract
The Automata Processor (AP) developed by Micron Semiconductor is a fundamentally new hardware computing architecture capable of performing high-speed, comprehensive search and analysis of complex, unstructured data streams. A highly scalable fabric of interconnected processing elements, the AP delivers unprecedented, energy efficient parallelism while avoiding many of the complexities inherent in standard parallel programming. The Automata Processor is especially powerful because it implements natively in hardware the non-deterministic finite automata (NFA) paradigm from classic computer science theory. The non-determinism property allows many states to be active at once. This allows the AP to explore many potential candidate matches in parallel, thus making it capable of solving "fuzzy" matching problems, even those with combinatorial search spaces. In this regard, it bears some similarity to quantum computing. The AP is particularly effective at leveraging this property thanks to its large capacity. A single chip holds over 49,000 states, all of which are concurrently scanning and responding to the input stream; and Micron's initial boards will hold 32 chips, thus providing over 1.5 million states, all operating concurrently. The speaker is co-director of the UVA Center for Automata Processing (CAP) co-founded by Micron Semiconductor and the University of Virginia for fostering fundamental research on foundations and applications of automata computing.

Short Biography of Dr. Mircea Stan

Mircea R. Stan received the Ph.D. (1996) and the M.S. (1994) degrees in Electrical and Computer Engineering from the University of Massachusetts at Amherst and the Diploma (1984) in Electronics and Communications from "Politehnica" University in Bucharest, Romania. Since 1996 he has been with the Charles L. Brown Department of Electrical and Computer Engineering at the University of Virginia, where he is now a professor. Prof. Stan is teaching and doing research in the areas of high-performance low-power VLSI, temperature-aware circuits and architecture, embedded systems, spintronics, and nanoelectronics. He leads the High-Performance Low-Power (HPLP) lab and is a co-director of the Center for Automata Processing (CAP). He has more than eight years of industrial experience, has been a visiting faculty at UC Berkeley in 2004-2005, at IBM in 2000, and at Intel in 2002 and 1999. He has received the NSF CAREER award in 1997 and was a co-author on best paper awards at ISQED 2008, GLSVLSI 2006, ISCA 2003 and SHAMAN 2002. He was the chair of the VLSI Systems and Applications Technical Committee (VSA-TC) of IEEE CAS in 2005-2007, general chair for ISLPED 2006 and for GLSVLSI 2004, technical program chair for NanoNets 2007 and ISLPED 2005, and on technical committees for numerous conferences. He is a Senior Editor for the IEEE Transactions on Nanotechnology since 2014, and was an AE for the IEEE Transactions on Nanotechnology in 2012-2014, IEEE Transactions on Circuits and Systems Systems I in 2004-2008 and for the IEEE Transactions on VLSI Systems in 2001-2003. He has also been a Guest Editor for the IEEE Computer special issue on Power-Aware Computing in December 2003 and a Distinguished Lecturer for the IEEE Circuits and Systems (CAS) Society in 2012-2013 and 2004-2005, and for the Solid-State Circuits Society (SSCS) in 2007-2008. Prof. Stan is a fellow of the IEEE, a member of ACM, and also of Eta Kappa Nu, Phi Kappa Phi and Sigma Xi. His current h-index is 43 and i10-index is 101.

Dr. Sandip Kundu
Professor of Electrical and Computer Engineering
Tel: (413) 577-3309, E-mail: kundu@ecs.umass.edu, Website: http://www.ecs.umass.edu/~kundu
University of Massachusetts, Amherst, USA


Abstract
Device reliability and manufacturability have emerged as dominant concerns in end-of-road CMOS and emerging nanotechnology devices. An increasing number of hardware failures are attributed to manufacturability or reliability problems. ITRS vision been described as:
“Relaxing the requirement of 100% correctness for devices and interconnects may dramatically reduce costs of manufacturing, verification, and test. Such a paradigm shift is likely forced in any case by technology scaling, which leads to more transient and permanent failures of signals, logic values, devices, and interconnects.”
Maintaining an acceptable manufacturing yield for chips containing tens of billions of transistors with wide variations in device parameters has been identified as a great challenge. Additionally today's nanoscale devices suffer from accelerated aging effects because of the extreme operating temperature and electric fields they are subjected to. Unless addressed in design, aging-related defects can significantly reduce lifetime of a product.
In this talk, we will discuss microarchitectural techniques for improving yield and reliability of homogeneous chip multiprocessors (CMP). The key concepts involve a hardware framework to enables utilizing the redundancies inherent in a multi-core system to keep the system operational in face of partial failures. We engage the existing resources to implement spatial and temporal redundancy. Such a service improves yield and reliability, at a slight loss of performance.
We will present results to show the feasibility and practicality of the solutions.

Short Biography of Dr. Sandip Kundu

Sandip Kundu is a Professor at the University of Massachusetts at Amherst. Prior to joining academia, he spent several years in industry: first as a Research Staff Member at IBM Research Division and then at Intel Corporation as a Principal Engineer. He has published over 200 research papers in VLSI design and test and holds several key patents including ultra-drowsy sleep mode in processors, and has given more than a dozen tutorials at various conferences. He is a Fellow of the IEEE, Fellow of the Japan Society for Promotion of Science (JSPS) and a Distinguished Visitor of the IEEE Computer Society. He is currently an Associate Editor of the ACM Transactions on Design Automation of Electronic Systems. Previously, he has served as an Associate Editor of the IEEE Transactions on Computers and the IEEE Transactions on VLSI systems. He is/was the Technical Program Chair of ICCD in 2000, Asian Test Symposium in 2011, ISVLSI in 2012 and 2014, DFTS 2014 and General chair of ICCD in 2001, VLSI Design Conference in 2005, DFTS in 2015.

iNIS Committees

Saraju Mohanty, University of North Texas, USA (Chair)

Prasun Ghosal, Indian Institute of Engineering Science and Technology, Shibpur, India (Vice Chair)

Dhruva Ghai, Oriental University, India (Vice Chair)

Aida Todri-Sanial, CNRS-LIRMM, France

Ashok Srivastava, Louisiana State University, USA

Helen Li, University of Pittsburg, USA

Himanshu Thapliyal, University of Kentucky, USA

Jia Di, University of Arkansas, USA

Nabanita Das, Indian Statistical Institute, India

Sudeep Pasricha, Colorado State University, USA

Xin Li, Carnegie Mellon University, USA

General Chairs:

Saraju P. Mohanty, University of North Texas, USA

Dhruva Ghai, Oriental University, India

Program Chairs:

Ashok Srivastava, Louisiana State University, USA

Shiyan Hu, Michigan Technological University, USA

Prasun Ghosal, Indian Institute of Engineering Science and Technology, Shibpur, India

Publication Chair:

Himanshu Thapliyal, University of Kentucky, USA

Web Chair:

Mike Borowczak, Erebus Labs & Consulting LLC, USA

Publicity Chairs:

Sudeep Pasricha, Colorado State University, USA

Aida Todri-Sanial, CNRS-LIRMM, France

Shanq-Jang Ruan, National Taiwan University of Science & Technology, Taiwan

Vaskar Raychoudhury, Indian Institute of Technology Roorkee, India

Local Arrangement Chair:

Pallavi Khosa, Oriental University, India

Rishab Pareek, Oriental University, India

Special Session Chairs:

Xin Li, Carnegie Mellon University, USA

Siva Yellampalli, UTL Technologies, India

Student Forum Chairs:

Anirban Sengupta, Indian Institute of Technology Indore, India

Bishnu P. Das, Indian Institute of Technology Roorkee, India

Finance Chair:

Garima Thakral, Oriental University, India

Registration Chair:

Hare Ram Singh, Oriental University, India

The Technical Program Committee Is Divided Into Six Tracks

Nanoelectronic VLSI and Sensor Systems (NVS):
Chairs
Jawar Singh, IIITDM Jabalpur, India
Yiyu Shi, Missouri University of Science and Technology, USA
Members
Ajit Khosla, University of Calgary, Micro-Engineering Dynamics Automation Lab
Amir Zjajo, Delft University of Technology
Arnab Datta, Indian Institute of Technology, Roorkee
Balwinder Raj, NIT Jalandhar, India
B. R. Singh, Indian Institute of Information Technology, Allahabad
Bharat Joshi, University of North Carolina at Charlotte
Bibhudutta Rout, University of North Texas
Brajesh K. Kaushik, Indian Institute of Technology, Roorkee
Dheeraj Sharma, IIITDM Jabalpur
Durga Misra, New Jersey Institute of Technology
Elias Kougianos, University of North Texas
Gaillardon Pierre-Emmanuel, EPFL
Ganesh Balakrishnan, University of New Mexico
Mary L. Regeena, BITS-Pilani, Dubai
Oghenekarho Okobiah, Samsung Semiconductor
Rohit Sharma, Indian Institute of Technology Ropar
Ruchir Gupta, IIITDM Jabalpur
S. S. Rajput, National Physical Laboratory
Samaresh Das, Indian Institute of Technology, Delhi
Santanu Mishra, Indian Institute of Technology, Kanpur
Satinder K Sharma, Indian Institute of Technology, Mandi
Shubhajit Roy Chowdhury, Indian Institute of Information Technology Hyderabad
Soumya Pandit, University of Calcutta
Sudhir Chandra, Indian Institute of Technology, Delhi
Yu Cao, Arizona State University

Energy-Efficient, Reliable VLSI Systems (ERS):
Chairs
Manisha Pattanaik, ABV-IITM, Gwalior, India
Saket Srivastava, University of Lincoln, UK
Members
Baris Taskin, Drexel University
Dhireesha Kudithipudi, Rochester institute of technology
Geng Zheng, Analog Devices, Inc.
Karthikeyan Lingasubramanian, University of Alabama at Birmingham
Lionel Torres, University of Montpellier 2
Manish Goswami, Indian Institute of Information Technology, Allahabad
Mohammad Hashmi, IIITD
Muhammad Shafique, Fakultät für Informatik
Nagi Mekhiel, Ryerson University
Nagi Naganathan, Avago Technologies
Oleg Garitselov, Spectracom Corporation
Paul Ezhilchelvan, Newcastle University, Newcastle upon Tyne
Preeti Ranjan Panda, Indian Institute of Technology Delhi
Rajeevan Chandel, NIT Hamirpur
Sajal K Paul, Indian School of Mines, Dhanbad
Samrat Sabat, University of Hyderabad
Saqib Khursheed, University of Liverpool
Sujay Deb, IIIT Delhi
Xiaoqing Wen, Kyushu Institute of Technology

Hardware/Software Solutions for Big Data (SBD):
Chairs
Theocharis Theocharides, University of Cyprus, Cyprus
Rajiv Ranjan, Commonwealth Scientific and Industrial Research Organization (CSIRO), Australia
Members
Chang Liu, CSIRO
Christos-Savvas Bouganis, Imperial College
Dan Chen, Wuhan University
Daniel Sun, Leeds University
Debajyoti Mukhopadhyay, Maharashtra Institute of Technology
Dhaval Thakker, Leeds University
Dongxi Liu, CSIRO
Dzmitry Kliazovich, University of Trento
Fethi Rabhi, University of New South Wales
Ivona Brandic, Vienna University of Technology
Jie Tao, Karlsruhe Institute of Technology
Laurence Yang, St. Francis Xavier University
Lizhe Wang, Chinese Academy of Sciences
Madhu Mutyam, IIT Madras
Malay Bhattacharyya, Indian Institute of Engineering Science and Technology (IIEST), Shibpur
Mazin Yousif, Royal Dutch Shell Global
Miranda Zhang, Australian National University
Paul Watson, University of Newcastle
Prem Jayaraman, CSIRO
Rodrgio Calheiros, University of Melbourne
Sanjay Patel, IBM
Saurabh Garg, Univeristy of Tasmania
Tejal Shah, University of New South Wales
Vijay Degalahal, Intel
Yang Xiang, Deakin University

Hardware/Software for Internet of Things (IOT):
Chairs
Vaskar Raychoudhury, Indian Institute of Technology Roorkee, India
Gustavo Marfia, University of Bologna, Italy, Visiting Scholar, UCLA, USA
Members
Atul Negi, University of Hyderabad
Balwinder Raj, National Institute of Technology Jalandhar
Bhaskar Sardar, Jadavpur University
Chi-Chia Sun, National Formosa University
Daqiang Zhang, Tongji University, China
Debasish Jana, FIE, FIETE, TEOCO Software Pvt Ltd
Dhaval Patel, Indian Institute of Technology, Roorkee
Niranjan Ray, National Institute of Technology Rourkela, India
Plaban Kumar Bhowmik, Indian Institute of Technology Kharagpur
Prabin Padhy, Indian Institute of Information Technology, Design and Manufacturing Jabalpur
Sarah Gallacher, University College London (UCL), UK
Sarbani Roy, Jadavpur University
Satish Singh, Indian Institute of Information Technology Allahabad
Subhadip Basu, Jadavpur University
Yu Hua, Huazhong University of Science and Technology, China 
Yu Huang, Nanjing University, China
Zakirul Alam Bhuiyan, Central South University, China 

Hardware for Secure Information Processing (SIP):
Chairs
Kailash Chandra Ray, Indian Institute of Technology Patna, India
Kamalakanta Mahapatra, National Institute of Technology, Rourkela, India
Members
Amit Acharyya, Indian Institute of Technology, Hyderabad
Anand Bulusu, Indian Institute of Technology Roorkee
Apostolos Fournaris, Technological Educational Institute of Western Greece
Ashis Kumar Mal, National Institute of Technology Durgapur
Bibhas Chandra Dhara, Jadavpur University
Brajesh Kumar Kaushik, Indian Institute of Technology Roorkee
Christos Kyrkou, University of Cyprus
Debotosh Bhattacharjee, Jadavpur University
Devesh Dwivedi, Systems And Technology Group, IBM India
Julian Jang-Jaccard, CSIRO
Kun-Lin Tsai, TungHai University
Manikandan Palanichamy, LIRMM, France
Mridul Sankar Barik, Jadavpur University
Nicolas Sklavos, University of Patras, Greece
Santosh Biswas, Indian Institute of Techology, Guwahati
Santosh Kumar Vishvakarma, Indian Institute of Technology, Indore
Sarbani Palit, Indian Statistical Institute
Satyajeet Nimgaonkar, Cisco Systems, Inc.

Cyber Physical Systems and Social Networks (CSN):
Chairs
Qi Zhu, University of California, Riverside, USA
Madhavi Ganapathiraju, University of Pittsburgh, USA
Members
Abhishek Srivastava, IIT Indore
Amitabha Bagchi, Indian Institute of Technology Delhi
Chung-Wei Lin, University of California, Berkeley
Debapriyo Majumdar, Indian Statistical Institute Kolkata
Fei Miao, University of Pennsylvania
Gourinath Banda, Indian Institute of Technology Indore
Jason Xue, City University of Hong Kong
Karan Mitra, Luleå University of Technology
Kevin Irick, Pennsylvania State University
Mehdi Maasoumy, University of California, Berkeley
Mianxiong Dong, Muroran Institute of Technology
Qing-Shan Jia, Tsinghua University
Rudra Mohan Tripathy, Silicon Institute of Technology, Bhubaneswar
Surya Nepal, CSIRO
Yanzhi Wang, University of Southern California
Yi Deng, Virginia Polytechnic Institute and State University
Zonghua Gu, Zhejiang University

Event Sponsors / become a sponsor today!

Technical Co-Sponsors

Sponsorship of an international conferences represent an organization's innovations, developments, and capabilities the world of eminent scientists and engineers who are from academia and industry. The opportunities of iNIS sponsorship are available on a first-come, first-served basis. So organization are advised to reserve the opportunity that spotlights the organization's name. The following table gives a summary of benefits that possibly an organization can get at iNIS.
  • In addition to the items below, other negotiable sponsorship is possible on case-to-case basis. The objective to encourage maximum participation and get maximum support from community of scholars.
  • In case of common item of interest, higher sponsorship package sponsors will be given the first preference, if applicable.
  • Logos to be provided by the sponsor as per conference's specifications; All content for display material, banners, backdrops, advertisements, to be put up as part of sponsorships collaterals, will have to be supplied by the sponsors, in the formats required, within the timelines specified.
  • The payments may be in US$ or Indian National Rupee (INR). With sponsors taking care of and responsible for ensuring prevailing conversion rates - from whatever currency into Indian rupees, on the day of remittance.

Silicon Level

  1. The sponsor's name would be displayed synonymously with iNIS.
  2. Appropriately sized logo on the side panels of the backdrop on stage(s), along with other applicable logos.
  3. Logo on the conference badge, along with the conference logo
  4. Logo on the conference bag, along with the conference logo
  5. Logo on sponsors’ choice item FCFS, from: Conference mug, pen, water bottle, visiting Card Holder
  6. Registration fee will be waived off for upto 12 delegates from the sponsor.
  7. Coverage in print media as per conference's publicity plan that gets to be in place.

Minimum Sponsorship Level of US$8,000.

Platinum Level

  1. The sponsor would be considered as an associate sponsor and its name would be displayed on every poster of iNIS.
  2. Appropriately sized logo on the side panels of the backdrop on stage(s), along with other applicable logos.
  3. Registration fee will be waived off for upto 8 delegates from the sponsor.
  4. Coverage in print media as per conference's publicity plan that gets to be in place.

Minimum Sponsorship Level of US$6,000.

Gold Level

  1. The sponsor would be a co-sponsor and its name would be displayed on every poster of the INIS.
  2. Appropriately sized logo on the side panels of the backdrop on stage(s), along with other applicable logos.
  3. Registration fee will be waived off for upto 6 delegates from the sponsor.
  4. Coverage in print media as per conference's publicity plan that gets to be in place.

Minimum Sponsorship Level of US$4,000.

Silver Level

  1. Appropriately sized logo on the side panels of the backdrop on stage(s), along with other applicable logos.
  2. Registration fee will be waived off for upto 4 delegates from the sponsor.
  3. Coverage in print media as per conference's publicity plan that gets to be in place.

Minimum Sponsorship Level of US$2,000.

Bronze Level

  1. Appropriately sized logo on the side panels of the backdrop on stage(s), along with other applicable logos.
  2. Registration fee will be waived off for upto 2 delegates from the sponsor.
  3. Coverage in print media as per conference's publicity plan that gets to be in place.

Minimum Sponsorship Level of US$1,000.
Become a sponsor

Silicon Level Sponsor/ Oriental University

iNIS 2015 will be held at the Oriental University in Indore, India. More details forthcoming. In the meantime feel free to visit their website.

Visit Site

Silver Level Sponsors

IEEE Circuits and Systems Society (IEEE-CAS) Outreach Initiative.

Bronze Level Sponsors

The Venues/ What to do, Where to stay & Where to go

What to do in Indore!

Places to visit in and around Indore, Madhya Pradesh Madhya Pradesh is a centrally located state of India. The name “madhya” literally means central and “pradesh” implies region or state. This state is situated exactly in the heart of the country with no coastline or international borders. Madhya Pradesh has a rich history reflected in its ancient temples, fortresses, and cave works. There are several large cities in this state, with Bhopal as its capital. General information of Madhya Pradesh tourism is available here.

Places to see in Indore

Indore, is one of the major cities of Madhya Pradesh. This city is the commercial center of an agricultural region where several cash crops are produced. The city is the site of several palaces and institutions of higher learning. Indore was founded in 1715, and rose to prominence under the Maratha dynasty of Holkars. In 1818, it become a British protectorate and made capital of the princely state of Indore. Indore was later merged with Madhya Bharat in 1948. Following are some of the places to visit in Indore. More information may be found here Looking for more?

1. Where to Stay

Effotel Hotel Indore, Plot No. 10-C/ C.A., Scheme No. 94, Sector C, Indore, India 452010, Phone: +91 731 474 0000.

iNIS 2015 organizers strongly suggest delegates/authors to book rooms at the this hotel as rooms are blocked for the meeting.
Rate: The negotiated rates for the event is the following:
  • Single occupancy - $40 or INR 2500 + taxes
  • Double occupancy - $50 or INR 3100 + taxes
  • Taxes - 11.20%

How to Book?
All the guests can book their rooms by sending their reservation details on reservations@effotelindore.com, mentioning their name, check in and check out dates, estimated time for arrival, single/double occupancy and also they need to mention that the booking is in reference of Oriental University to obtain the specially discounted rate.
Contact Details:
Pravir Sharma, Sales and Marketing Executive
Phone: + 91 731 400 6666, Mobile: +91 789 880 1331
Deadline to Book: 30 November 2015 (Monday)

Hotel Website Reservation Email Address

2. Hotel for the Meeting (Conference Venue)

Radisson BLU Hotel Indore, Scheme No 94 C, Ring Road, Indore - 452010, Indore, India,
Phone: +91 731 473 8888,
This is very close to Effotel Hotel where delegates will stay, 2min walking distance.

Venue Hotel Website

Travel/ Getting to Indore, Madhya Pradesh, India

By Air to Indore:

Devi Ahilyabai Holkar Airport (IDR) is a prominent airport in the Madhya Pradesh state of India and is about 8 km from the Indore city. It offers good connectivity from major cities of India like New Delhi, Mumbai, Bangalore, Ahmedabad, Hyderabad, Pune, Kolkata, Jabalpur, Bhopal, Nagpur, and Raipur. International travelers can get connecting flights to Indore from Delhi (800 km) or Mumbai (655 km) airport. There are at least 6 airlines operating in Indore: Air India, Jet Airways, SpiceJet, Jet Lite, Indigo and Kingfisher.

By Rail to Indore:

Indore Junction Railway Station (INDB) is an important railway station in Western railway zone. It is well connected to major Indian cities like Mumbai, Pune, Nagpur, Delhi, Jaipur, Agra, Ahmedabad,Vadodara, Howrah, Bhopal, Ujjain, Gwalior, Bhind, Jabalpur, Bilaspur, Khandwa, Lucknow, Varanasi, Patna, Ambala Ct, Jammu, Dehradun and Trivandrum. Indore is well connected to Delhi and Mumbai by rail. There is a daily Malwa Express to Delhi from Indore (807 km), via Ujjain (55 km), Bhopal (186 km), Jhansi (475 km), Gwalior (486 km), and Agra (604 km). The Avantika Express leaves every day in the afternoon for Mumbai (16 hours and 593 km). The other broad-gauge line connects Indore to Ujjain, Bhopal, and Jabalpur (494 km). There is also an Intercity Express between Indore and Bhopal and the travel time is 5 1/2 hours. There is also a meter-gauge track from Indore to Khandwa, Ratlam and Jaipur (647 km).

Event Location

iNIS
Oriental University
Opposite Revati Range Gate No.1,
Sanwer Road, Jakhya,
Indore, Madhya Pradesh 453555, India

email

Get Directions

Contact Us / Questions/Comments/Suggestions