"The iSES 2020 organizing committee recognizes the global emergency due to Coronavirus disease (COVID-19). In the unlikely scenario that the current situation prolongs, iSES 2020 will allow virtual presentations like Skype, recorded ppt, YouTube video, etc. as replacement of actual in person presentation for authors who cannot travel to Chennai, India. All the accepted papers registered and presented either in-person or virtually will appear in the iSES 2020 proceedings and IEEE Xplore. We will continue to monitor the situation, and update you as things change on a daily basis." “Selected papers from iSES 2020 program will be invited to special issues of IEEE Consumer Electronics Magazine and Springer Nature Computer Science Journal” Keynotes – IEEE-iSES 2020

Keynotes



Prof. Massimo Alioto
National University of Singapore, Singapore



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Biography: Massimo Alioto is with the ECE Department of the National University of Singapore, where he leads the Green IC group and the Integrated Circuits and Embedded Systems area. Previously, he held positions at the University of Siena, Intel Labs – CRL (2013), University of Michigan - Ann Arbor (2011-2012), University of California – Berkeley (2009-2011), EPFL - Lausanne. He is (co)author of 270+ publications on journals and conference proceedings, and three books with Springer. His primary research interests include ultra-low power circuits and systems, self-powered integrated systems, near-threshold circuits for green computing, widely energy-scalable integrated systems, circuits for machine intelligence, hardware security, and emerging technologies. He is the Editor in Chief of the IEEE Transactions on VLSI Systems, and was Deputy Editor in Chief of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems. Prof. Alioto was the Chair of the “VLSI Systems and Applications” Technical Committee of the IEEE CASS (2010-2012), Distinguished Lecturer (2009-2010), and members of the Board of Governors (2015-2020). He served as Guest Editor of numerous journal special issues, Technical Program Chair of several IEEE conferences (ISCAS 2022, SOCC, PRIME, ICECS, VARI, NEWCAS, ICM), and TPC member (ISSCC, ASSCC). Prof. Alioto is an IEEE Fellow.



Prof. Gautam Das

University of Texas at Arlington, USA

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Biography: Gautam Das is the Associate Dean for Research, College of Engineering, a Distinguished University Chair Professor of Computer Science and Engineering, and Director of the Database Exploration Laboratory (DBXLAB) of UT-Arlington. Prior to joining UTA in Fall 2004, Dr. Das has held positions at Microsoft Research, Compaq Corporation and the University of Memphis. He graduated with a B.Tech in computer science from IIT Kanpur, India, and with a Ph.D in computer science from the University of Wisconsin, Madison. He is a Fellow of the IEEE and a member of the ACM.
Dr. Das has broad research interests in all aspects of Big Data Exploration, including databases, data analytics, machine learning and data mining, search and retrieval, data privacy and security, and data ethics. His research has resulted in over 200 papers, many of which have appeared in premier data mining, database and algorithms conferences and journals. His work has received several awards, including the SIGMOD Research Highlights award in received in 2019, pVLDB Reproducibility award in 2018, IEEE ICDE 10-Year Influential Paper award in 2012, ACM SIGKDD Doctoral Dissertation Award (honorable mention) in 2014 for his recent student, Best Student Paper Award of CIKM 2013, VLDB Journal special issues on Best Papers of VLDV 2018, VLDB 2012 and VLDB 2007, Best Paper of ECML/PKDD 2006, and Best Paper (runner up) of ACM SIGKDD 1998. He has been a keynote speaker on several occasions such as at ICIT 2019, IEEE ICCA 2017, ExploreDB 2015, IEEE APWC 2014, WebDB 2012, DBRank 2012, and presented invited lectures, tutorials and courses at various universities, research labs, and conferences.
He has been on the Editorial Board of the journals ACM TODS and IEEE TKDE. He has served as General Chair of ACM SIGMOD/PODS 2018, ICIT 2009, Program Chair of COMAD 2008, CIT 2004 and SIGMOD-DMKD 2004, Best Paper Awards Chair of ACM SIGKDD 2006, as well as in program committees of numerous conferences. He has served as a Guest Editor for the ACM TKDD special issue devoted to the best papers of ACM SIGKDD 2006.
Dr. Das's research has been supported by grants from National Science Foundation, Army Research Office, Office of Naval Research, Department of Education, Texas Higher Education Coordinating Board, Qatar Foundation, AT&T, Microsoft Research, Nokia Research, Cadence Design Systems and Apollo Data Technologies.



Prof. Jim Plusquellic
University of New Mexico, USA


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Biography: Professor Plusquellic received both his M.S. and Ph.D. degrees in Computer Science from the University of Pittsburgh in 1995 and 1997, respectively. He is currently a Professor in Electrical and Computer Engineering at the University of New Mexico. His research interests are in the area of nano-scale VLSI and include security and trust in IC hardware, embedded system design, supply chain and IoT security and trust, silicon validation, design for manufacturability and delay test methods. Professor Plusquellic received an "Outstanding Contribution Award" from IEEE Computer Society in 2012 for co-founding and for his contributions to the Symposium on Hardware-Oriented Security and Trust (HOST), and again recently in 2017 for "Co-Founder of and providing Outstanding Contributions to the IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) for the Past Ten Years 2008-2017". He served as General Chair for HOST in 2010, for the Defect-Based Testing Workshop in 2006 and as Associate Editor for Transactions on Computers. He is currently serving as Editor-in-Chief of Hardware Security for Cryptography, MDPI, as Hardware Demonstration Chair at HOST and has been engaged in presenting IoT-based tutorials at HOST. He has recently been inducted into the HOST Hall-of-Fame and has authored or co-authored three book chapters for Springer Link on the topics of PUF-based Authentication and Hardware Trojan Detection. He received the "10 Years of Continuous Service Award" from the International Test Conference, a Best Paper Award from VTS, an ACM Distinguished Service Award from SIGDA and two Austin CAS Fellow Awards from IBM. He received the "Albuquerque lab-to-business accelerator" award in 2016, the "2014 Innovation Award" from the Science and Technology Center at the University of New Mexico, was a "Featured Entrepreneur" within the School of Engineering and has multiple patents and provisional applications filed with the US. Patent and Trademark Office. Professor Plusquellic is President and CEO of IC-Safety, LLC and is CTO for Enthentica Inc., both start-ups in the hardware security and trust space. He has recently fully developed two on-line courses in Hardware-Software Codesign for FPGAs (http://ece-research.unm.edu/jimp/codesign) and Hardware-Oriented Security and Trust (http://ece-research.unm.edu/jimp/HOST). He is serving or has served on the Program Committees for HOST, Design and Test in Europe, International Test Conference, International Conference on Computer-Aided Design and VLSI Test Symposium. He has published more than 70 refereed conference and journal papers. He is a Golden Core Member of the IEEE Computer Society.



Prof. Swarup Bhunia
University of Florida, USA


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Biography: Swarup Bhunia received his B.E. (Hons.) from Jadavpur University, Kolkata, India, and the M.Tech. degree from the Indian Institute of Technology (IIT), Kharagpur. He received his Ph.D. from Purdue University, IN, USA, in 2005. Currently, Dr. Bhunia is a preeminence professor and Steven Yatauro Faculty Fellow in the department of Electrical and Computer Engineering at University of Florida, Gainesville, FL, USA. Earlier, Dr. Bhunia has served as the T. and A. Schroeder associate professor of Electrical Engineering and Computer Science at Case Western Reserve University, Cleveland, OH, USA. He has over twenty years of research and development experience with over 250 publications in peer-reviewed journals and premier conferences and ten edited or authored books (two upcoming) in the area of VLSI design, CAD and test techniques. His research interests include low power and robust design, hardware security and trust, adaptive nanocomputing and novel test methodologies. He has worked in the semiconductor industry on RTL synthesis, verification, and low power design for about three years. Dr. Bhunia received IEEE-CS TCVLSI Distinguished Research Award (2018), IBM Faculty Award (2013), National Science Foundation (NSF) career development award (2011), Semiconductor Research Corporation (SRC) technical excellence award (2005) as a team member, best paper award in ACM Transactions on Design Automation of Electronic Systems (TODAES 2017), best paper award in IEEE BioMedical Circuits and Systems Conference (BioCAS 2016), best paper award in International Conference on VLSI Design (VLSI Design 2012), best paper award in International Conference on Computer Design (ICCD 2004), best paper award in Latin American Test Workshop (LATW 2003), and best paper nomination in Asia and South Pacific Design Automation Conference (ASP-DAC 2006) and in Hardware Oriented Test and Security (HOST 2010), nomination for John S. Diekhoff Award, Case Western Reserve University (2010) and SRC Inventor Recognition Award (2009).

Dr. Bhunia has been serving as founding editor-in-chief in Journal of Hardware and Systems Security (HaSS), an associate editor of IEEE Transactions on CAD (TCAD), IEEE Transactions on Multi-Scale Computing Systems (TMSCS), ACM Journal of Emerging Technologies (JETC), and Journal of Low Power Electronics (JOLPE). He has served as a guest editor of IEEE Design & Test of Computers (2010, 2013), IEEE Computer Magazine (2016), IEEE Transcation on CAD (2015), and IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2014). He has served as co-program chair of IEEE IMS3TW 2011, IEEE NANOARCH 2013, IEEE VDAT 2014, and IEEE HOST 2015, and in the technical program committee of Design Automation Conference (2014-2015), Design Automation and Test in Europe (DATE 2006-2010), Hardware Oriented Trust and Security Symposium (HOST 2008-2010), IEEE/IFIP International Conference on VLSI (VLSI SOC 2008), Test Technology Educational Program (TTEP 2006-2008), International Symposium on Low Power Electronics and Design (ISLPED 2007-2008), IEEE/ACM Symposium on Nanoscale Architectures (NANOARCH 2007-2010), IEEE International Conference on VLSI (ISVLSI 2008-2010), International Conference of VLSI Design as a track chair (2010) and in the program committee of International Online Test Symposium (IOLTS 2005). Dr. Bhunia has given tutorials on low-power and robust design and test in premier conference including International Test Conferences (ITC 2009), VLSI Test Symposium (VTS 2010), and Design Automation and Test in Europe (DATE 2009). He is a distingusihed ACM speaker and a senior member of IEEE.