Title : Enabling Always – On Sensor Nodes Entirely Powered by Sustainable.
Energy Sources – Making Our World Smarter and Greener.
Prof. Massimo Alioto, Ph.D., National University of Singapore, Singapore
ABSTRACT : Aggressive shrinkage of batteries and their ultimate replacement by sustainable energy sources is a crucial goal in the evolution of the Internet of Things (IoT), in view of the massive environmental impact of their production and disposal for the expected Trillion of IoT edge devices that will be deployed in the upcoming decade. Wide power-performance adaptation down to nWs is becoming crucial in always-on nearly real-time and energy-autonomous silicon systems that are subject to wide variability in the power availability and the performance target. Wide adaptation is indeed a prerequisite to assure continuous operation in spite of the widely fluctuating energy/power source (e.g., energy harvester), and to grant swift response upon the occurrence of events of interest (e.g., on-chip data analytics), while maintaining extremely low consumption in the common case. These requirements have led to the strong demand of systems having an extremely wide performance-power scalability and adaptation, so that they can relentlessly operate without interruption in spite of the highly-uncertain power availability.
In this talk, new directions to drastically extend the performance-power scalability of digital, analog and power management circuits and architectures are presented. New directions to achieve full-system coordinated power-performance scaling across all other sub-systems are also discussed. Silicon demonstrations and trends in the state of the art of battery-light, battery-less and battery-indifferent systems are illustrated to quantify the benefits offered by wide power-performance adaptation, identifying opportunities and challenges for the decade ahead. Finally, a mm-scale integrated system that operates uninterruptedly when solely powered by moonlight is demonstrated, paving the way to a new generation of always-on systems with little or no battery. This ultimately makes our world smarter through ubiquitous always-on edge devices, and greener through the exclusive adoption of sustainable energy sources.
Biography : Massimo Alioto is with the ECE Department of the National University of Singapore, where he leads the Green IC group, the Integrated Circuits and Embedded Systems area and the FD – Fabrics industry-sponsored lab on FD-SOI intelligent & connected systems. Previously, he held positions at the University of Siena, Intel Labs – CRL, University of Michigan – Ann Arbor, University of California – Berkeley, EPFL – Lausanne.
He is author of 300+ publications on journals and conference proceedings, and four books with Springer, including the popular “Enabling the Internet of Things – from Integrated Circuits to Integrated Systems”, which is the first book published in the area of integrated system design for the edge of the Internet of Things. His primary research interests include ultra-low power circuits and systems, self-powered integrated systems, near-threshold circuits for green computing, widely energy-scalable integrated systems, circuits for machine intelligence, hardware security, and emerging technologies.
He is the Editor in Chief of the IEEE Transactions on VLSI Systems, and was Deputy Editor in Chief of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems. Prof. Alioto is a Distinguished Lecturer for the IEEE Solid-State Circuits Society, after serving as Distinguished Lecturer for the Circuits & Systems Society. He served as Guest Editor of numerous journal special issues, Technical Program Chair of several IEEE conferences (ISCAS 2023, SOCC, PRIME, ICECS, VARI, NEWCAS, ICM), and TPC member (ISSCC, ASSCC). Prof. Alioto is an IEEE Fellow.
Title : Sensor Diversity and Scaling New Paradigm for Intelligent Systems
Prof. Navakanta Bhat, Ph.D., Indian Institute of Science, India
Abstract : Since the invention of the semiconductor transistor in 1947, the phenomenal progress in electronics systems is enabled by the transistor scaling in the micro to nano regime coupled with very large scale to giga scale integration, driven by storage and compute applications. Today, the complex electronic systems quite often achieve first pass success from concept to deployment, thanks to mature CAD tools that help manage very diverse building blocks, with hierarchy of abstraction. However, the basic tenet of transistor scaling is staring at the red brick wall, due to scientific and technological challenges. It is contemplated that non-CMOS architectures enabled by nanotechnology and heterogeneous integration must drive the Moore’s law in future and enable the intelligent systems, beyond the conventional scaling era.
I believe that the stage is now set for a new wave of electronic systems to be equipped with massive sensory functions, specifically with biological and chemical sensors, going beyond conventional compute and storage paradigm. However, not much attention is given to develop a holistic approach to manage the diversity and scaling issues of sensor blocks, akin to what was done in digital, analog and mixed signal electronics. I will present two case studies from our research: (i) Biosensor systems for point of care diagnostics : the story of managing the sensing of multiple analytes in blood and urine with an eventual goal to realize “Lab on Palm” (ii) Gas sensor systems for environmental monitoring, breath analysis and hazardous gas leakage detection, with an eventual goal to realize the “Electronic Nose”
With this backdrop, I will end my talk with some thoughts on future challenges in achieving highly complex and intelligent electronic sensory systems.
Biography : Navakanta Bhat received his Ph.D. in Electrical Engineering from Stanford University, Stanford, CA in 1996. Then he worked at Motorola’s Networking and Computing Systems Group under Advanced Products R&D Lab (APRDL) in Austin, TX until 1999. He joined the Indian Institute of Science, Bangalore in 1999 where he is currently Professor in the Centre for Nano Science and Engineering. He is also the Dean of Interdisciplinary Sciences at IISc. His current research is focused on Nanoelectronics device technology, Biosensors for point of care diagnostics and Gas sensors for pollution monitoring. He has over 300 research publications in international journals and conferences and over 30 US patents to his credit. He is an elected Fellow of the Indian National Academy of Engineering and an elected Fellow of IEEE. He has received several awards for his research achievements, including the prestigious Infosys Prize (2018) for contributions in Engineering and Computer Science. He is a member of the Board of Governors of the IEEE Electron Devices Society and also the Chair of Nanotechnology technical committee. He is a Distinguished Lecturer of the IEEE Electron Devices Society. He was the Editor of IEEE Transactions on Electron Devices, (2013-2015), and the chief-editor of the IEEE TED special issue on “2D Materials for Electronic, Optoelectronic and Sensors”. He was the technical program chair for the International Conference on VLSI design and Embedded Systems in 2007. He was the Chairman of the Human Resource Development and Infrastructure committee of the National Program on Micro and Smart Systems and was the member of the committee set up by the Principal Scientific Adviser to Govt. of India to recommend strategies to develop semiconductor manufacturing ecosystem in India. He is the founder and promoter of a startup company, PathShodh Healthcare Pvt Ltd (www.pathshodh.com). Based on his group’s research in biosensors, PathShodh has developed the first of its kind multi-analyte point-of-care diagnostic device for 5 blood tests and 3 urine tests, related to multiple chronic diseases including diabetes and its complications, anemia and malnutrition, kidney and liver diseases. For this technology, PathShodh has received multiple recognitions.
Title : Scalable Signal Reconstruction for a Broad Range of Applications by Leveraging Database Techniques.
Prof. Yiran Chen, Ph.D., Duke University, USA
Abstract : The rapid growth of modern neural network (NN) models’ scale generates ever-increasing demands for high computing power of artificial intelligence (AI) systems. Many specialized computing devices have been deployed in the AI systems, forming a truly application-driven heterogeneous computing platform. In this talk, we discuss the importance of hardware/software co-design in AI system designs. We first use resistive memory based NN accelerators to illustrate the design philosophy of AI computing systems, and then present several hardware-friendly NN model compression techniques. We also extend our discussions to distributed AI systems and briefly introduce the automation of NN co-design flow, e.g., neural architecture search.
Biography : Yiran Chen received B.S and M.S. from Tsinghua University and Ph.D. from Purdue University in 2005. After five years in industry, he joined University of Pittsburgh in 2010 as Assistant Professor and then promoted to Associate Professor with tenure in 2014, held Bicentennial Alumni Faculty Fellow. He now is the Professor of the Department of Electrical and Computer Engineering at Duke University and serving as the director of NSF Industry–University Cooperative Research Center (IUCRC) for Alternative Sustainable and Intelligent Computing (ASIC) and co-director of Duke University Center for Computational Evolutionary Intelligence (CEI), focusing on the research of new memory and storage systems, machine learning and neuromorphic computing, and mobile computing systems. Dr. Chen has published one book and more than 400 technical publications and has been granted 96 US patents. He serves or served the associate editor of several IEEE and ACM transactions/journals and served on the technical and organization committees of more than 50 international conferences. He is now serving as the Editor-in-Chief of IEEE Circuits and Systems Magazine. He received 7 best paper awards, 1 best poster award, and 15 best paper nominations from international conferences and workshops. He is the recipient of NSF CAREER award, ACM SIGDA outstanding new faculty award, the Humboldt Research Fellowship for Experienced Researchers, and the IEEE SYSC/CEDA TCCPS Mid-Career Award. He is the Fellow of IEEE, the Distinguished Member of ACM, the distinguished lecturer of IEEE CEDA, and is listed in the HPCA Hall of Fame.
Title : Scalable Signal Reconstruction for a Broad Range of Applications by Leveraging Database Techniques
Prof. Gautam Das, Ph.D., University of Texas at Arlington, USA
Abstract : The Signal Reconstruction Problem (SRP) is an important optimization problem where the objective is to identify a solution to an under-determined system of linear equations that is closest to a given prior. It has a substantial number of applications in diverse areas, including network traffic engineering, medical image reconstruction, acoustics, astronomy, and many more. Unfortunately, most of the common approaches for solving SRP do not scale to large problem sizes. In our work, we use several seemingly unrelated techniques from database research, including similarity joins, materialization and reuse, to develop signal reconstruction algorithms that scale to orders of magnitude larger than previously studied. Our work has been appeared as research highlights in recent ACM SIGMOD as well as Communications of the ACM.
Biography : Dr. Gautam Das is the University of Texas at Arlington’s College of Engineering Associate Dean for Research, a Distinguished University Chair Professor of Computer Science and Engineering, and Director of the Database Exploration Laboratory (DBXLAB). Prior to UTA, Dr. Das held positions at Microsoft Research, Compaq Corporation and the University of Memphis. He graduated with a B.Tech in computer science from IIT Kanpur, India, and with a Ph.D in computer science from the University of Wisconsin-Madison. He is a Fellow of the IEEE and a member of the ACM.
Dr. Das’ research has investigated broadly all aspects of Big Data Exploration, including databases, data analytics, machine learning and data mining, search and retrieval, data privacy and security, and data ethics. His research has resulted in over 200 papers, many of which have appeared in premier data mining, database and algorithms conferences and journals. His work has received several awards, including CACM Research highlights, SIGMOD Research Highlights, IEEE ICDE 10-Year Influential Paper, and several others. He has been on the editorial boards of the journals ACM TODS and IEEE TKDE, and as General Chair of ACM SIGMOD/PODS 2018. Dr. Das’ research has received international, national, state, and industry support from the National Science Foundation, Army Research Office, Office of Naval Research, U.S. Department of Education, Texas Higher Education Coordinating Board, Qatar Foundation, AT&T, Microsoft Research, Nokia Research, Cadence Design Systems and Apollo Data Technologies.
Title : Innovations in IoT for a Safe, Secure, and Sustainable Future
Prof. Swarup Bhunia, Ph.D., University of Florida, USA
Abstract : Internet of Things (IoT) promises to usher in the fourth industrial revolution through an exponential growth of smart connected devices deployed in myriad application domains. It gives rise to new relationships between man and smart connected machines that might transform our everyday experiences. Such a transformation, however, builds on innovations at all levels in the IoT architecture – from edge devices to the cloud. In this talk, we will cover the IoT design practices and core technological challenges that need to be addressed to enable widespread deployment of IoT. We will focus on innovations in the areas of energy-efficiency, security, interoperability and intelligent decision making. Next, we will discuss several compelling applications of IoT that give unprecedented capability to us. In particular, we will cover applications of IoT in addressing some of the critical safety, security, and sustainability issues in our society.
Biography : Swarup Bhunia received his B.E. (Hons.) from Jadavpur University, Kolkata, India, and the MTech. degree from the Indian Institute of Technology (IIT), Kharagpur. He received his Ph.D. from Purdue University, IN, USA in 2005. Currently, Dr. Bhunia is a preeminent professor, director of the Warren B. Nelms Institute for the Connected World and Semmoto Chair Professor of Internet of Things in the department of Electrical and Computer Engineering at University of Florida, Gainesville, FL, USA. Earlier, Dr. Bhunia has served as the T. and A. Schroeder associate professor of Electrical Engineering and Computer Science at Case Western Reserve University, Cleveland, OH, USA. He has over twenty years of research and development experience with over 250 publications in peer-reviewed journals and premier conferences and ten edited or authored books (two upcoming) in the area of VLSI design, CAD and test techniques. His research interests include low power and robust design, hardware security and trust, adaptive nanocomputing and novel test methodologies. He has worked in the semiconductor industry on RTL synthesis, verification, and low power design for about three years. Dr. Bhunia received IEEE-CS TCVLSI Distinguished Research Award (2018), IBM Faculty Award (2013), National Science Foundation (NSF) career development award (2011), Semiconductor Research Corporation (SRC) technical excellence award (2005) as a team member, best paper award in ACM Transactions on Design Automation of Electronic Systems (TODAES 2017), best paper award in IEEE BioMedical Circuits and Systems Conference (BioCAS 2016), best paper award in International Conference on VLSI Design (VLSI Design 2012), best paper award in International Conference on Computer Design (ICCD 2004), best paper award in Latin American Test Workshop (LATW 2003), and best paper nomination in Asia and South Pacific Design Automation Conference (ASP-DAC 2006) and in Hardware Oriented Test and Security (HOST 2010), nomination for John S. Diekh off Award, Case Western Reserve University (2010) and SRC Inventor Recognition Award (2009). Dr. Bhunia has been serving as founding editor-in-chief in Journal of Hardware and Systems Security (HaSS), an associate editor of IEEE Transactions on CAD (TCAD), IEEE Transactions on Multi-Scale Computing Systems (TMSCS), ACM Journal of Emerging Technologies (JETC), and Journal of Low Power Electronics (JOLPE). He has served as a guest editor of IEEE Design & Test of Computers (2010, 2013), IEEE Computer Magazine (2016), IEEE Transaction on CAD (2015), and IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2014). He has served as co-program chair of IEEE IMS3TW 2011, IEEE NANOARCH 2013, IEEE VDAT 2014, and IEEE HOST 2015, and in the technical program committee of Design Automation Conference (2014-2015), Design Automation and Test in Europe (DATE 2006-2010), Hardware Oriented Trust and Security Symposium (HOST 2008-2010), IEEE/IFIP International Conference on VLSI (VLSI SOC 2008), Test Technology Educational Program (TTEP 2006-2008), International Symposium on Low Power Electronics and Design (ISLPED 2007-2008), IEEE/ACM Symposium on Nanoscale Architectures (NANOARCH 2007-2010), IEEE International Conference on VLSI (ISVLSI 2008-2010), International Conference of VLSI Design as a track chair (2010) and in the program committee of International Online Test Symposium (IOLTS 2005). Dr. Bhunia has given tutorials on low-power and robust design and test in premier conference including International Test Conferences (ITC 2009), VLSI Test Symposium (VTS 2010), and Design Automation and Test in Europe (DATE 2009). He is a distinguished ACM speaker and a senior member of IEEE.
Title : Smart and Secure Electronic Cash.
Prof. Jim Plusquellic, Ph.D., University of New Mexico, USA
Abstract : Electronic money or e-Cash is becoming increasingly popular as the preferred strategy for making purchases, both on- and off-line. Several unique attributes of e-Cash are appealing to customers, including the convenience of always having “cash-on-hand” without the need to periodically visit the ATM, the ability to perform peer-to-peer transactions without an intermediary, and the peace of mind associated in conducting those transactions privately. Equally important is that paper (fiat) money provides customers with an anonymous method of payment, which is highly valued by many individuals. Although anonymity is implicit with fiat money, it is a difficult property to preserve within e-Cash schemes. Beyond anonymity, e-Cash systems must also provide a secure transaction mechanism to guard against counterfeiting, fraud, and double spending. In this talk, I will discuss several protocols that we have developed and tested that leverage the security properties of a physical unclonable function (PUF). A PUF is a hardware security primitive that is capable of providing an unlimited supply of secret keys and bit strings for authentication and encryption operations within an e-Cash message exchange protocol. Our PUF-cash protocols also integrate reinforcement learning algorithms to increase the robustness of the protocols’ security properties, adding a “smart” layer of defense against adversarial attacks.
Biography : Professor Plusquellic received both his M.S. and Ph.D. degrees in Computer Science from the University of Pittsburgh in 1995 and 1997, respectively. He is currently a Professor in Electrical and Computer Engineering at the University of New Mexico. His research interests are in the area of Nano – scale VLSI and include security and trust in IC hardware, embedded system design, supply chain and IoT security and trust, silicon validation, design for manufacturability and delay test methods. Professor Plusquellic received an “Outstanding Contribution Award” from IEEE Computer Society in 2012 for co-founding and for his contributions to the Symposium on Hardware Oriented Security and Trust (HOST), and again recently in 2017 for “Co-Founder of and providing Outstanding Contributions to the IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) for the Past Ten Years 2008-2017”. He served as General Chair for HOST in 2010, for the Defect-Based Testing Workshop in 2006 and as Associate Editor for Transactions on Computers. He is currently serving as Editor-in-Chief of Hardware Security for Cryptography, MDPI and as Program Chair for HOST 2019 and 2020. He has recently been inducted into the HOST Hall-of-Fame and has authored or co-authored three book chapters for Springer Link on the topics of PUF-based Authentication and Hardware Trojan Detection. He received the “10 Years of Continuous Service Award” from the International Test Conference, a Best Paper Award from VTS, an ACM Distinguished Service Award from SIGDA and two Austin CAS Fellow Awards from IBM. He received the “Albuquerque lab-to-business accelerator” award in 2016, the “2014 Innovation Award” from the Science and Technology Center at the University of New Mexico, was a “Featured Entrepreneur” within the School of Engineering and has multiple patents and provisional applications filed with the US. Patent and Trademark Office. Professor Plusquellic is President and CEO of IC-Safety, LLC and is CTO for Enthentica Inc., both start-ups in the hardware security and trust space. He is a Golden Core Member of the IEEE Computer Society.