Smart Healthcare - Cybersecurity Perspectives
Dr. Saraju P. Mohanty
Department of Computer Science and Engineering University of North Texas, Denton, TX 76207, USA.
Abstract:
The healthcare system has evolved from traditional healthcare to smart healthcare with relentless research in the last few decades. The importance of the smart healthcare involving telemedicine, connected health, and mobile health cannot be overstated. Smart healthcare built using Internet-Medical-Things (IoMT) is a key component in smart cities and smart villages which can provide effective and optimal healthcare to the patients even with limited healthcare personnel. Smart healthcare is further expanding with the help of healthcare Cyber-Physical System (H-CPS) that integrates IoMT, electronic health record (EHR), and artificial intelligence (AI). H-CPS consists of various components including, biosensors, body sensors, electronics, wearables, implantables, networks, middleware, firmware, software, EHR, and AI. The integrated technologies like IoMT, connectivity, and AI bring additional challenges to H-CPS including attacks on IoMT-devices, healthcare data, and counterfeit medicines. This talk will present detailed insight of IoMT based smart healthcare built as a H-CPS. It will discuss the cybersecurity challenges and solutions specific to the H-CPS/IoMT. The talk will address many questions about smart healthcare including: (1) What is H-CPS/IoMT? (2) What are the challenges of H-CPS/IoMT? (3) What are the cybersecurity solutions for H-CPS/IoMT? (4) What is Security-by-Design for H-CPS? (5) What are SbD solutions for H-CPS? (6) How to ensure counterfeit-free pharmaceutical supply chain?
Speaker Biography:
Dr. Saraju P. Mohanty is a Professor at the University of North Texas. Prof. Mohanty’s research is in “Smart Electronic Systems” which has been funded by NSF, SRC, US Air Force, IUSSTF, and Mission Innovation. He has over 20 years of research experience on security and protection of media, hardware, and system. He introduced the Secure Digital Camera (SDC) in 2004 with built-in security features designed using Security by Design (SbD) principle. He is widely credited as the designer for the first digital watermarking chip in 2004 and first the low-power digital watermarking chip in 2006. He has authored 450 research articles, 5 books, and 10 granted and pending patents. His Google Scholar h-index is 53 and i10-index is 226 with 12,000 citations. He is a recipient of 16 best paper awards, Fulbright Specialist Award in 2020, IEEE Consumer Electronics Society Outstanding Service Award in 2020, the IEEE-CS-TCVLSI Distinguished Leadership Award in 2018, and the PROSE Award for Best Textbook in Physical Sciences and Mathematics category in 2016. He has delivered 16 keynotes and served on 14 panels at various International Conferences. He has been serving on the editorial board of several peer-reviewed international journals, including IEEE Transactions on Bigdata, IEEE Transactions on CAD as well as EiC of IEEE Consumer Electronics Magazine. He served as the Chair of the IEEE-CS Technical Committee on VLSI (TCVLSI) during 2014-2018 and served on the Board of Governors of the IEEE Consumer Electronics Society during 2019-2021. He is the steering committee chair/vice-chair for the IEEE International Symposium on Smart Electronic Systems (iSES), the IEEE-CS Symposium on VLSI (ISVLSI), and the OITS International Conference on Information Technology (OCIT). He has mentored 3 post-doctoral researchers, and supervised 15 Ph.D. dissertations, 26 M.S. theses, and 12 undergraduate projects.
Security and Privacy of Machine Learning Systems
Sandip Kundu
Department of Electrical & Computer Engineering University of Massachusetts Amherst
Abstract
Deep Neural Networks (DNNs) are widely used for prediction and classification tasks. However, they are vulnerable to a variety of threats, including model extraction, evasion and inversion attacks. Model extraction attacks steal DNN models, which is a threat to intellectual property, data privacy, and security. Model evasion attack manipulates an input to a machine learning model in such a way that the model makes an incorrect prediction. In model inversion attack, an adversary attempts to infer sensitive or private information about the training data or individual data points that were used to train the model by exploiting the model’s outputs. We will describe simplified mathematical formulation of the problems and conclude the talk with various approaches for defending against adversarial attack on ML system.
Biography
Sandip Kundu is a Professor of Electrical and Computer Engineering at the University of Massachusetts Amherst. Until recently, he was also a program director at the National Science Foundation wit hin the CISE directorate. Kundu began his career at IBM Research as a
Research Staff Member; then worked at Intel Corporation as a Principal Engineer before joining UMass Amherst as a professor in 2005. He has published nearly 300 research papers in VLSI d esign and test, holds several key patents including ultra – drowsy sleep mode in processors, and has given more than a dozen tutorials at various conferences. He is a Fellow of the IEEE, Fellow of the Japan Society for Promotion of Science (JSPS), Senior Int ernational Scientist of the Chinese Academy of Sciences and was a Distinguished Visitor of the IEEE Computer Society. He has been an Associate Editor of the IEEE Transactions on Dependable and Secure Computing. Associate Editor of the IEEE Transactions on Computers, IEEE Transactions on VLSI Systems and ACM Transactions on Design Automation of Electronic Systems. He has been Technical Program Chair/General Chair of multiple conferences including ICCD, ATS, ISVLSI, DFTS and VLSI Design Conference.Automated Polynomial Formal Verification: Human-Readable Proof Generation
Rolf Drechsler
University of Bremen/DFKI, Germany
Abstract
In the past years, the importance of the verification of digital circuits has increased significantly, as their complexity has grown. Simulation techniques cannot fully guarantee their correctness, as the correctness has to be shown for every possible input assignment. Thus, formal verification has to be applied. However, formal verification methods may require exponential time and space in the worst case. Therefore, Polynomial Formal Verification (PFV) has been researched in the past years, where polynomial upper bounds have been proven for the formal verification and by this guarantee efficient run times of the tools. Polynomial bounds have been proven successfully for the verification of several adders, multipliers and other circuits. However, due to the lack of automation techniques, all previous proofs were conducted manually. Thus, a tool enabling the automatic proof generation has recently been introduced, which demonstrates the concept of automatic proofs on the example of BDDs. We enhance the tool to automatically generate an extended human-readable proof, detailing the automatic reasoning, such that the produced proof is fully comprehensible.
Biography
Rolf Drechsler received the Diploma and Dr. phil. nat. degrees in computer science from the Johann Wolfgang Goethe University in Frankfurt am Main, Germany, in 1992 and 1995, respectively. He worked at the Institute of Computer Science, Albert-Ludwigs University, Freiburg im Breisgau, Germany, from 1995 to 2000, and at the Corporate Technology Department, Siemens AG, Munich, Germany, from 2000 to 2001.
Since October 2001, Rolf Drechsler is a Full Professor and Head of the Group of Computer Architecture, Institute of Computer Science, at the University of Bremen, Germany. In 2011, he additionally became the Director of the Cyber-Physical Systems Group at the German Research Center for Artificial Intelligence (DFKI) in Bremen. His current research interests include the development and design of data structures and algorithms with a focus on circuit and system design. He is an ACM Distinguished Member and an IEEE Fellow.
From 2008 to 2013 he was the Vice Rector for Research and Young Academics at the University of Bremen. Since 2018 he is the Dean of the Faculty of Mathematics and Computer Science.
Rolf Drechsler was a member of Program Committees of numerous conferences including e.g., DAC, ICCAD, DATE, ASP-DAC, FDL, MEMOCODE, and FMCAD. He was Symposiums Chair at ISMVL 1999 and 2014, and the Topic Chair for “Formal Verification” at DATE 2004, DATE 2005, DAC 2010, and DAC 2011 and 2018. He was the General Chair of the IEEE European Test Symposium 2018 and the Program Chair of ICCAD 2020. He received best paper awards at the Haifa Verification Conference (HVC) in 2006, the Forum on specification & Design Languages (FDL) in 2007, 2010 and 2020, the IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) in 2010, the Euromirco Digital System Design Conference 2020 and the IEEE/ACM International Conference on Computer-Aided Design (ICCAD) in 2013 and 2018. He received the Berninghausen Award for Excellence in Teaching in 2018.
He is a co-founder of the Graduate School of Embedded Systems and he is the coordinator of the Graduate School “System Design” funded within the German Excellence Initiative. He is a co-founder and the spokesperson of the Data Science Center at the University of Bremen.
Rolf Drechsler served as an Associate Editor of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Very Large Scale Integration Systems, Chip, IET Cyber-Physical Systems: Theory & Applications, International Journal on Multiple-Valued Logic and Soft Computing, and ACM Journal on Emerging Technologies in Computing Systems.
Transforming Cloud Infrastructure for the AI era
Navin Bishnoi
India Country Manager, and AVP CCS (Compute & Custom Solutions)
Abstract
Generative AI is taking the world by storm and unleashing the imagination of millions of people with exciting new applications and use cases for individuals and organizations. Enabling these applications need a huge hardware infrastructure, which needs to scale at fast pace, while keeping energy requirements in control. Join me to hear about HW components, scale-up and care-about, to be ready for AI era.
Biography
Navin is India Country Manager and AVP Compute & Custom Solutions at Marvell India. As the India Country Manager, he oversees all business operations to deliver and continue to grow / improve, as well as represents the company externally. As an engineering head, he leads Compute and Custom ASIC Design for Infrastructure domain (covering Networking, Processor, Cloud, Automotive and AI/ML applications). Prior to this, he has worked with IBM, Freescale, Cadence, and TI for automotive, consumer and custom ASIC designs. He had received his bachelor’s degree in Electronics and Communication from NIT Surathkal. He has been an active member in EDA standards, Conferences, and Industry associations, to enable semiconductor eco-system development initiatives in India. He is the Founding member of ITC India and TTTC India, to drive the growth of DFT/Test in India Semiconductor Eco-system and served as General Chair of ITC India for first 5 years. He is part of advisory committee for Karnataka state skilling committee as well as India Semiconductor Mission R&D eco-system committee.
Breaking the Thermal and Power Delivery Walls for 3DIC
Mircea R. Stan
Director of Computer Engineering
Abstract
The semiconductor industry is poised to continue the historic Moore’s law trend of doubling the level of integration every few years, even as the rate of doubling has slowed down and the virtuous cycle benefits of Dennard scaling have vanished. Once devices no longer scale laterally, the only way to continue to increase areal density is by going vertical using 2.5D and 3D integration. For now the community has embraced chiplets and interposer-based 2.5D solutions, and in the near future is poised to move ahead to 3DIC. However, 3DIC raises several fundamental difficulties in addition to the clear fabrication challenges: as the number of physical layers in a 3D-IC stack increases, from the present 2.5D multi-layer solutions (with an interposer, or only a couple of layers), to true 3D many-layer stacks, the energy cycle problem of delivering power to and removing heat from the 3D stack become daunting. The fundamental reason for these thermal and power delivery walls is the mismatch between the volumetric (cubic) power consumption and heat dissipation in 3DIC, and the areal (quadratic) power delivery and heat removal through a 2D surface (top and/or bottom of the 3D stack). As the number of layers in a 3DIC becomes larger so does the mismatch between 3D consumption and heat dissipation and 2D power delivery and cooling. This talk will present a framework to provide fundamental solutions to the 3DIC thermal and power delivery walls that are also practical.
Biography
Mircea R. Stan is teaching and doing research in the areas of AI hardware, Processing in Memory, Cyber-Physical Systems, Computational RFID, spintronics, and nanoelectronics. He is Director of Computer Engineering, leads the High-Performance Low-Power (HPLP) lab and is an associate director of the Center for Automata Processing (CAP). Prof. Stan received the Ph.D. (1996) and the M.S. (1994) degrees from UMass Amherst and the Diploma (1984) from the Politehnica University in Bucharest, Romania. Since 1996 he has been with the ECE Department at UVa, where he is now the Virginia Microelectronics Consortium (VMEC) endowed chair. He was a visiting faculty at UC Berkeley in 2004-2005, at IBM in 2000, and at Intel in 2002 and 1999. He received the 2018 Influential ISCA Paper Award (For 2003 paper “Temperature-aware microarchitecture”), the NSF CAREER award in 1997 and was a co-author on best paper awards at ASILOMAR19, LASCAS19, SELSE17, ISQED08, GLSVLSI06, ISCA03 and SHAMAN02 and IEEE Micro Top Picks in 2008 and 2003. He is Editor-in-Chief for the IEEE TVLSI and was Senior Editor for the IEEE TNano (2014-2023). Prof. Stan is a fellow of the IEEE, a member of ACM, and of Eta Kappa Nu, Phi Kappa Phi and Sigma Xi.
Leveraging Spintronic Devices for Neuromorphic and Signal Processing at Edge of Network
Ronald F. DeMara
Department of Electrical and Computer
Engineering
University of Central
Florida
Abstract
In neuromorphic and signal processing applications, minimizing the chip area footprint while increasing energy efficiency, remain as vital foci for pushing intelligent computation towards the edge of the network. To do so, it is possible to leverage new opportunities to interweave various signal processing and AI computational demands via circuit datapaths that hybridize use of CMOS and spintronic devices. Spin-based datapaths employ a variety of commercialized devices such as Spin-Transfer Torque Magnetic Tunnel Junctions (STT-MTJs) and emerging devices such as Spin-Orbit Torque MTJs (SOT-MTJs). Representative STT-MTJ and SOT-MTJ circuits for Compressive Sensing (CS) and Machine Learning (ML) which were developed over the last decade will be presented and assessed for the key challenges facing the design of future IoT sensors within targeted CS/ML applications. This talk will address promising circuit-level and architectural-level approaches to hybridizing analog and digital computation, adding non-volatility to datapaths, and increasing tuneability while reducing area demand and wire count.
Biography
Ronald F. DeMara is Pegasus Professor in the Department of Electrical and Computer Engineering, and joint faculty member of Computer Science, at the University of Central Florida, where he has been a full-time faculty member since 1993. His interests are in computer architecture, post-CMOS devices, and reconfigurable fabrics. He has applied these to autonomous, embedded, and intelligent/neuromorphic systems, on which he has completed over 325 articles, 50 funded projects as PI, and completed 56 graduates as Ph.D. dissertation and/or M.S. thesis advisor. He has served ten terms as a Topical Editor or Associate Editor including IEEE Transactions on Computers, Transactions on Emerging Topics in Computing, Transactions on VLSI, IEEE Spectrum, and Technical Program Committees of various IEEE conferences including General Co-Chair of GLSVLSI-2023. He received the Joseph M. Biedenbach Outstanding Engineering Educator Award from IEEE and is a Fellow of AAAS.