Brain Inspired Computing : The Extraordinary Voyages in Known and Unknown Worlds
Hai “Helen” Li
Clare Boothe Luce Professor and Associate Department Chair
Department of Electrical and Computer Engineering
Duke University, Durham NC 27708, USA
Homepage : http://cei.pratt.duke.edu/ Email : hai.li@duke.edu
Abstract:
Human brain is the most sophisticated organ that nature ever builds. Building a machine that can function like a human brain, indubitably, is the ultimate dream of a computer architect. Although we have not yet fully understood the working mechanism of human brains, the part that we have learned in past seventy years already guided us to many remarkable successes in computing applications, e.g., artificial neural network and machine learning. Inspired by the working mechanism of human brain, neuromorphic system naturally possesses a massively parallel architecture with closely coupled memory, offering a great opportunity to break the “memory wall” in von Neumann architecture. The talk will start with a background introduction of neuromorphic computing, followed by examples of hardware acceleration schemes of learning and neural network algorithms and memristor-based computing engine. I will also share our prospects on the future technology challenges and advances of neuromorphic computing.
Speaker Biography:
Dr. Hai “Helen” Li received her bachelor’s and master’s degrees from Tsinghua University, China, and her Ph.D. degree from Purdue University, USA. She is the Clare Boothe Luce Professor and Associate Chair of the Electrical and Computer Engineering Department at Duke University. Before that, she was with Qualcomm Inc., San Diego, CA, USA, Intel Corporation, Santa Clara, CA, Seagate Technology, Bloomington, MN, USA, the Polytechnic Institute of New York University, Brooklyn, NY, USA, and the University of Pittsburgh, Pittsburgh, PA, USA. Her research interests include neuromorphic computing systems, machine learning and deep neural networks, memory design and architecture, and cross-layer optimization for low power and high performance. She has authored or co-authored more than 250 technical papers in peer-reviewed journals and conferences and a book entitled Nonvolatile Memory Design: Magnetic, Resistive, and Phase Changing (CRC Press, 2011). She received 9 best paper awards and an additional 9 best paper nominations from international conferences. Dr. Li serves/served as an Associate Editor of a number of IEEE/ACM journals. She was the General Chair or Technical Program Chair of multiple IEEE/ACM conferences. Dr. Li is a Distinguished Lecturer of the IEEE CAS society (2018-2019) and a distinguished speaker of ACM (2017-2020). Dr. Li is a recipient of the NSF Career Award, DARPA Young Faculty Award (YFA), TUM-IAS Hans Fischer Fellowship from Germany, and ELATE Fellowship (2020). Dr. Li is an IEEE fellow and a distinguished member of the ACM.
Privacy and Security in Wearable Wound Sensors : Advances and Perspectives
Shekhar Bhansali
Department of Electrical & Computer Engineering
Florida International University, Miami, FL
Electrical Communication and Cyber Systems (ECCS)
National Science Foundation, Alexandria, VA
Email: sbhansa@fiu.edu
Abstract :
Wounds that do not heal over long periods of time (3 months) are classified as Chronic wounds. They manifest themselves in patients that have underlying diseases like poorly controlled diabetes. Chronic wounds need to be managed to prevent complications, preserve tissue function, and facilitate healing. Current practice for wound evaluation and wound management includes visually recording the wound area and wound depth to assess healing progress. The need to visit a clinic at least once every week results in poor patient compliance and long-term complication with inferior health outcomes.
Our research focuses on leveraging advances in electrochemical sensing, fabrication techniques and electronics to develop a new class of affordable wound dressings that enable quantitative measurements of markers of wound healing. As these sensors mature real world issues of privacy and security is the use of these sensors arise. The challenge of balancing costs and usability in context of usability and privacy are discussed.
Bio-Sketch :
Shekhar Bhansali, PhD, is Lucent CALA Technologies Distinguished University Professor of Electrical and Computer Engineering at Florida International University. He also serves as Division Director (Electrical, Communications and Cyber Systems), National Science Foundation. Dr. Bhansali received his Ph.D. in Electrical Engineering from RMIT University in Australia (1997). As a mentor, Dr. Bhansali has advised over 22 postdocs, 65 Ph.D. and master’s students, and more than 130 undergraduate/high school students. Dr. Bhansali is the recipient of Alfred P. Sloan Foundation Mentor of the Year Award, ECS Sensors Division Outstanding Achievement Award, and the NSF CAREER Award. He is Fellow of AAAS, NAI, IOP and AIMBE.
Silicon Photonics for Deep Learning Acceleration in Smart Electronic Systems
Sudeep Pasricha
Department of Electrical and Computer Engineering
Colorado State University, Fort Collins, CO, 80523, USA
Homepage: http://www.engr.colostate.edu/~sudeep/
Email: sudeep@colostate.edu
Abstract :
The massive data deluge from mobile, IoT, and edge devices, together with powerful innovations in data science and hardware processing, have established deep learning as the cornerstone of emerging smart electronic systems in the medical, automotive, industrial automation, and consumer electronics domains. Domain-specific VLSI deep learning accelerators such as Google’s TPU, Apple’s Bionic, and Intel’s Nirvana, now dominate CPUs and GPUs for energy-efficient deep learning processing. However, these electronic accelerators are facing fundamental limits due to the slowdown of Moore’s law and their reliance on metal wires, which have well-known bandwidth and latency limitations. Silicon photonics represents a promising post-Moore technological alternative to overcome the limitations of electronic processing platforms. Not only can photonic interconnects fabricated in CMOS-compatible processes provide near speed of light transfers at the chip-scale, but photonic devices can now also be leveraged to perform computations entirely in the optical domain. In this talk, I will present my vision of how silicon photonics can be used to design an entirely new class of deep learning hardware accelerators that can provide orders of magnitude improvements over conventional electronic accelerators. I will discuss the evolution of silicon photonics over the past two decades, from integrated optics to photonic devices that can now be fabricated with low-cost CMOS-compatible manufacturing techniques. I will then cover new directions in power minimization, variation tolerance, fault resilience, and security for communication and computation with silicon photonics. I will share experiences from my journey over the past decade and a half towards the goal of realizing viable silicon photonic networks and computing substrates. I will end the talk with a discussion of the key challenges and opportunities to achieve unparalleled performance and energy-efficiency gains in future smart electronic systems with silicon photonics enabled acceleration.
Biography :
Sudeep Pasricha received the B.E. degree in Electronics and Communication Engineering from Delhi Institute of Technology, India, in 2000, after which he spent several years working for STMicroelectronics, India/France, and Conexant, USA. He received his Ph.D. degree in Computer Science from the University of California, Irvine in 2008. He joined Colorado State University in 2008 where he is currently a Walter Scott Jr. College of Engineering Professor in the Department of Electrical and Computer Engineering. He is also the Chair of Computer Engineering and the Director of the Embedded, High Performance, and Intelligent Computing (EPIC) Laboratory. His research broadly focuses on software algorithms, hardware architectures, and hardware-software co-design for energy-efficient, fault-tolerant, real-time, and secure computing, for embedded, IoT, and cyber-physical systems. Prof. Pasricha has published more than 200 papers in peer-reviewed journals and conferences that have received 7 best paper awards and 6 best paper nominations. He has filed for multiple patents, and co-authored several books and book chapters. His contributions have been recognized with several awards, including the George T. Abell Outstanding Research Faculty Award, IEEE-CS/TCVLSI Mid-Career Research Achievement Award, IEEE/TCSC Award for Excellence for a Mid-Career Researcher, AFOSR Young Investigator Award, ACM Technical Leadership Award, and ACM SIGDA Distinguished Service Award. He is currently a Senior Associate Editor for the ACM Journal of Emerging Technologies in Computing, and an Associate Editor for the ACM Transactions on Embedded Computing Systems, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Consumer Electronics, and IEEE Design & Test of Computers. He is also the Steering Committee Chair of IEEE Transactions on Sustainable Computing. He has served as General Chair and Technical Program Chair of 12 conferences, Steering and Organizing Committee Member of 40 conferences, and Technical Program Committee Member of 100+ conferences. He is an IEEE Senior Member and an ACM Distinguished Member.
Digital Storage and Memory for AI – From the Edge to the Data Center
Tom Coughlin
Coughlin Associates, Atascadero, CA, USA
Homepage: http://www.tomcoughlin.com
Email: tom@tomcoughlin.com
Abstract :
Applying AI at the edge and endpoints often requires working under non-data center environments and in power constrained conditions. AI inference also requires significant memory to hold weighting values from training. New non-volatile memories can help provide more memory in a given device die and use less power than NOR flash, SRAM or DRAM. This presentation will talk about changes in the memory/storage hierarchy and how it will change memory and storage in data centers and embedded devices to support energy efficient and low latency AI applications.
Biography :
Tom Coughlin, President, Coughlin Associates is a digital storage analyst and business and technology consultant. He has over 40 years in the data storage industry with engineering and senior management positions at several companies. Coughlin Associates consults, publishes books and market and technology reports (including The Media and Entertainment Storage Report and an Emerging Memory Report), and puts on digital storage-oriented events. He is a regular storage and memory contributor for forbes.com and M&E organization websites. He is an IEEE Fellow, Candidate for IEEE President Elect this year, Past-President of IEEE-USA, Past Director of IEEE Region 6 and Past Chair of the Santa Clara Valley IEEE Section, board member of the Consultants Network of Silicon Valley and is also active with SNIA and SMPTE. For more information on Tom Coughlin and his publications and activities go to www.tomcoughlin.com.
AI driven intelligent systems for medical diagnosis of brain and heart diseases
Ram Bilas Pachori
Department of Electrical Engineering
Indian Institute of Technology Indore, Indore, 453552, India.
Homepage: https://www.iiti.ac.in/people/~pachori/, Email: pachori@iiti.ac.in
Abstract:
The physiological signals namely electroencephalogram (EEG) and electrocardiogram (ECG) signals are commonly used for diagnosis of brain and heart diseases, respectively. The doctors generally perform diagnosis of based on visual inspection of these physiological signals. Such type of diagnosis procedure is very time-consuming specially for long-data recordings. Moreover, such diagnosis approach is subjective in nature and requires an expertise or training. Signal processing methods together with artificial intelligence (AI) techniques can help in designing intelligent systems for the automated diagnosis of brain and heart diseases based on these physiological signals. Such AI driven intelligent systems can help doctors in their diagnosis. Moreover, such intelligent systems can detect the diseases at initial level so that timely treatment can be carried out. The various methods which are based on signal processing and machine learning for the brain and heart diseases will be presented in this talk.
Speaker Biography:
Ram Bilas Pachori received the B.E. degree with honours in Electronics and Communication Engineering from Rajiv Gandhi Technological University, Bhopal, India in 2001, the M.Tech. and Ph.D. degrees in Electrical Engineering from Indian Institute of Technology (IIT) Kanpur, Kanpur, India in 2003 and 2008, respectively. He was a Postdoctoral Fellowship Holder at Charles Delaunay Institute, University of Technology of Troyes, Troyes, France during 2007-2008. He has been working as a faculty member at Department of Electrical Engineering, IIT Indore, India since 2009. During this period, he has served as an Assistant Professor (2009-2013), as an Associate Professor (2013-2017), and as a Professor since 2017. He is an Associate Editor of Electronics Letters, IEEE Transactions on Neural Systems and Rehabilitation Engineering, Biomedical Signal Processing and Control journals and an Editor of IETE Technical Review journal. He is a senior member of IEEE and a Fellow of IETE and IET. He has served as member of review boards for more than 100 scientific journals. He has also served in the scientific committees of various national and international conferences. He has delivered more than 200 talks and lectures in conferences, workshops, short term courses, and academic events organized by various institutes. He has been listed in the top h-index scientists in the area of Computer Science and Electronics by Research.com website (April, 2020). He has been listed in the world’s top 2 % scientists in the study carried out at Stanford University, USA (October, 2020). He has received several awards including Achievement Award (IICAI conference, 2011), Best Paper Award (ICHIT conference, 2012), Best Research Paper Awards (IIT Indore, 2015 & 2016), Premium Awards for Best Papers (IET Science, Measurement & Technology journal, 2019 & 2020), and IETE Prof. SVC Aiya Memorial Award (2021). He has supervised 14 Ph.D., 20 M.Tech., and 41 B.Tech. students for their theses and projects. He has 235 publications which include journal papers (145), conference papers (66), books (06), and book chapters (18). He has garnered around over 9400 citations with h-index of 52 (Google Scholar, October 2021). He has worked on various research projects with funding support from SERB, DST, DBT, and CSIR.
Application-Specific Quantum Circuits (ASQCs) for Image Processing
Himanshu Thapliyal
Department of Electrical Engineering and Computer Science
University of Tennessee, Knoxville, TN, USA
Web: https://www.eecs.utk.edu/people/himanshu-thapliyal/
Email: hthapliyal@utk.edu
Abstract:
A quantum algorithm can be defined as an algorithm that runs on a realistic model of quantum computation such as a quantum circuit model of computation. Furthermore, application-specific circuit designs are the essence of any computing system. Quantum circuits of arithmetic operations are vital in designing quantum hardware for Shor’s factoring algorithm, solving discrete log problem and quantum cryptanalysis, securing cryptosystems, and circuit design of quantum algorithms such as the class number and triangle finding algorithms. Further, quantum arithmetic circuits for addition, multiplication, division are widely used in quantum algorithms for quantum image processing including image orientation problems, image pattern recognition, and image template matching. In this talk, I will start with an overview of quantum computing. I will discuss quantum gates and resource cost measurements used to evaluate circuits made from these gates. The types of errors in noisy intermediate-scale quantum (NISQ) will be discussed. Later, I will discuss quantum circuits for various arithmetic functions such as addition, subtraction, integer multiplication, division taking into consideration multi-metric constraints such as the size of the circuit, depth of the circuit, the number of qubits in the circuit. Finally, I will discuss the use of quantum arithmetic to design application-specific quantum circuits (ASQCs) for image processing.
Biography:
Himanshu Thapliyal is currently an Associate Professor with the Department of Electrical Engineering and Computer Science at the University of Tennessee, Knoxville, TN, USA. He received a PhD degree in Computer Science and Engineering from the University of South Florida, Tampa, in 2011 where he received the ‘Distinguished Graduate Achievement Award’. From 2012-14, he worked as a designer of processor test solutions at Qualcomm, where he received the Qualcomm QualStar Award for contributions to memory built-in self-test. He joined as an Assistant Professor at the University of Kentucky, Lexington in 2014 where he got promoted to Associate Professor in 2020. He has been ranked in the top 50 among scientists throughout the world in the field of ‘Computer Hardware and Architecture’ for the calendar Years 2019 and 2020. He is the recipient of the 2019 NSF CAREER award and the 2020 IEEE-CS TCVLSI Mid-Career Research Achievement Award. He has authored over 150 journal/conference articles with over 4700 citations (h-index of 40), 3 US Patents and received Best Paper awards at the 2021 IEEE International Conference on Consumer Electronics (ICCE), 2020 IEEE World Forum on Internet of Things, 2017 Cyber and Information Security Research Conference (CISR) and 2012 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). He is serving as the Section Editor of the Springer Nature Computer Science and is leading two sections. He is Senior Associate Editor of the IEEE Consumer Electronics Magazine, Associate Editor of the IEEE Internet of Things Journal, and the editorial board member of the Microelectronics Journal. He co-founded the International Workshop on Quantum Computing: Circuits Systems Automation and Applications (QC-CSAA). His students have received several awards including Best Papers, outstanding PhD and Master’s student awards, and secured positions in companies such as Google, Apple, Intel, Cadence, Microsoft.
Hardware Based Verification and Methodologies for Modern SoCs
Sudhanshu Jayaswal
Senior Engineering Manager, Scalable Verification Systems
Siemens EDA, Noida, India
Homepage: https://eda.sw.siemens.com Email: sudhanshu_jayaswal@mentor.com
Abstract:
Verification is like what a cook does during the cooking process. He keeps tasting the food every now and then to make sure all the parameters are still intact. Verification is exactly like this. It compares intent with implementation at every step – corrects things if necessary and moves on. In Context of Modern SoCs having billions of gates, multi-cores and memory systems, sub-system IPs, Firmware working in coordination with System Software and Applications, verification challenges are quite diverse across system. For example, consider functional verification of a mobile SoC with an application like Angry Bird running over it. In this session we will learn about associated challenges and Industry prevalent methods using Hardware Based verification solutions to make this feasible.
Speaker Biography:
Sudhanshu graduated in Electronics and Communication Engineering from SGSIST Indore and pursued specialization in Integrated Electronics Circuit Design at IIT Delhi during his M.Tech. Sudhanshu Jayaswal is Senior Engineering Manager at Siemens EDA, Noida, India. Prior to this Sudhanshu has worked in C-DoT (Center for Development of Telematics), Agilent Technologies and Nvidia. Sudhanshu has 20 years of experience in the field of Design and Verification of Protocol IPs. He is veteran of PCIe Technology and has over 15 years of affiliation in this area and has successfully delivered various HW solutions in this widely used technology. Sudhanshu is active in solving problems associated with HW based Verification complexities and challenges faced by chip designers by developing various emulation solutions around complex system protocols like PCIe, CXL, 5G, SAS/SATA, Optical Transport Networking, and Ethernet. Sudhanshu is co-inventor in 2 patents filed in area of developing emulation solutions system for ethernet commercially known as Veloce Networking Application.