IEEE-iSES
16-18 December 2024, New Delhi, India
Prof. Niraj Jha
Department of Electrical and Computer Engineering, Princeton University, USA.
Title
A Bottom-up Medical Superintelligence Framework
Abstract
The artificial intelligence (AI) industry is currently focused on achieving superintelligence in a top-down fashion by training a very large (hundreds of billions to trillions of parameters) omniscient multimodal model using a large language model (LLM) as the base. This approach is insatiably thirsty for data during training, leading to unsustainable CO2 emissions. Even after incurring such huge computational and energy costs, these models are known to hallucinate. This makes it difficult to employ such models in domains where accuracy is important, e.g., smart healthcare. We propose to take the opposite tack – build medical superintelligence bottom-up, modeled after how superintelligence is achieved in the human society. Each of us just has human intelligence, but a society of humans achieves superintelligence in a bottom-up fashion by looking at the problem from diverse angles. Could we build medical superintelligence in the same bottom-up fashion through a society of medical AI assistants and AI agents? The AI assistants will serve as aides to health professionals. AI agents will have more autonomy. They need to be accompanied by a robust reasoning framework, e.g., counterfactual (what-if) reasoning. The current top-down approach to developing AI agents is based on using LLMs for reasoning. However, LLMs exhibit a very uneven reasoning performance. Our medical superintelligence framework will take inspiration from neuroscience and include episodic and working memories to facilitate reasoning. The AI assistants in our superintelligence framework will be based on fine-tuned foundation models, targeted at various modalities, e.g., physiological signals, medical images, and medical text, that can be trained data-efficiently and are aligned with each other. The initial goals of the framework are accurate disease detection, individual well-being, interpretability of AI predictions, and personalized medical decision-making. In this talk, we will explore our initial progress towards realizing this vision.
Speaker Biography
Niraj K. Jha received his B.Tech. degree in Electronics and Electrical Communication Engineering from Indian Institute of Technology, Kharagpur, India in 1981 and Ph.D. degree in Electrical Engineering from University of Illinois at Urbana-Champaign in 1985. He is a Professor of Electrical and Computer Engineering at Princeton University. He has served as an Associate Director for the Princeton Andlinger Center for Energy and the Environment. He is a Fellow of IEEE and ACM. He was given a Distinguished Alumnus Award by I.I.T., Kharagpur in 2014. He has co-authored five books among which are two textbooks that are being widely used around the world. He has served as the Editor-in-Chief of IEEE Transactions on VLSI Systems and as Associate Editor of several other IEEE Transactions. He is an author or co-author of more than 490 papers among which are 16 award-winning papers. His research interests include algorithms and architectures for machine learning, with applications to smart healthcare.
Prof. Susmita Sur-Kolay
Indian Statistical Institute, Kolkata.
Title
Design Automation for Quantum Computing Systems
Abstract
The two major drivers for quantum computing have been to overcome the limitations of classical deterministic digital computers in terms of both computational complexity and fabrication technology.
In this talk, we introduce the basic model of quantum computing. Next, we give a snapshot of algorithms for certain problems for which remarkable speed-up over classical computing has been achieved by quantum computing. Then, with a brief sketch of the progress in technology, we present specific challenges in design automation for quantum circuits comprising a cascade of error-prone gates.
Speaker Biography
Prof. Susmita Sur-Kolay received the B.Tech.(Hons.) degree in Electronics and Electrical Communications Engineering from Indian Institute of Technology Kharagpur and the Ph.D. degree in Computer Science and Engineering from Jadavpur University India. She has been a faculty member in the Advanced Computing and Microelectronics Unit of the Indian Statistical Institute, Kolkata, India since 1999 and is presently a Professor. During 1993-99, she was a Reader in the Department of Computer Science and Engineering of Jadavpur University. Before that, she was a post-doctoral fellow at University of Nebraska-Lincoln, and a Research Assistant at the Laboratory for Computer Science in Massachusetts Institute of Technology. She was also on sabbatical at Princeton University and Intel Corp., USA.
Her research contributions are in the areas of algorithmic design automation for VLSI physical design, fault modeling and testing, synthesis of quantum computers, and graph algorithms. She has co-authored several technical papers in leading international journals and refereed conference proceedings, and a chapter in the Handbook on Algorithms for VLSI Physical Design Automation. She was the Technical Program Co-Chair of the 18th International Conference on VLSI Design (2005), the 11th Symposium on VLSI Design and Test (2007), ISVLSI 2011 and has served on the program committees of several international conferences. She has served on the editorial board of the IET Computers and Digital Techniques, and IEEE Transactions on VLSI Systems. She is a Distinguished Visitor of IEEE Computer Society (India), Senior Member of IEEE, Fellow of Indian National Academy of Engineering, Member of ACM, IET and VLSI Society of India. Among other awards, she was the recipient of the President of India Gold Medal (summa cum laude) at IIT Kharagpur (1980), IBM Faculty Award (2009), Distinguished Alumnus Award (2020), Women in Technology Leadership from VLSI Society of India 2022.
Mr. Sanjay Gupta
CDO & Global Head of Engineering, L&T Semiconductor Technologies.
Title
Journey from Transistor to Chiplet: The Evolution of Semiconductor Innovation
Abstract
Semiconductors have been at the heart of technological progress, shaping industries and enabling transformative advancements. This keynote presentation takes you on a captivating journey from the humble beginnings of the transistor to the cutting-edge innovations of chiplets.
We will explore the foundational building blocks of electronics and its transition into the latest frontier in semiconductor technology “Chiplets” - the modular, scalable units which are transforming the way we design complex systems by enabling unprecedented flexibility, efficiency, and performance.
This talk will highlight the technological milestones, material innovations, and design breakthroughs that have propelled the semiconductor industry forward. It will also provide insights into how these advancements are addressing challenges in performance, power, and integration, paving the way for future applications across industries like automotive, AI, telecommunications, and beyond.
Speaker Biography
Sanjay Gupta is a seasoned semiconductor technology professional with more than 28 years in the global and hi-tech Industry and holds distinguished experience in the semiconductors, embedded software, and electronics system design. Sanjay started his career with Motorola as fresh college graduate - GET from Delhi College of Engineering in 1996 and rose up to become the Global Vice President of Engineering and Managing Director for NXP's Technical Innovation Centers. Later on he also did MBA from the Indian School of Business, Hyderabad with recognition in the Dean’s list. Prior to joining L&T Semiconductor, Sanjay was spearheading Minda Corporation’s Advanced Technologies Business vertical , as President & CEO Sanjay is known for collaborative leadership, building teams from scratch and passionately transforming teams from ‘Good to Great’ through Innovation programs, Strategic initiatives and through continuous improvement mindset.
Sanjay has been collaborating extensively with government bodies, industry stakeholders, and academic institutions for advancing the Indian Semiconductors & Electronics Ecosystem. He served as the Chairman and Board Member of the IESA Executive Council. He is also been a key advisory member to Govt (MeiTY) and member advisory board in various Industry Academia & Startup Incubator forums. Sanjay is Technologist at heart and holds multiple U.S. patents and numerous technical & business publications.
Prof. V. Ramgopal Rao
Group Vice-Chancellor, Birla Institute of Technology & Science (BITS) Pilani, India.
Title
TBA
Abstract
TBA
Speaker Biography
Prof. V. Ramgopal Rao, Vice Chancellor of BITS Pilani campuses since 2023, previously served as IIT Delhi's Director (2016-2021) and as a Chair Professor for Nanoelectronics at both IIT Bombay and IIT Delhi. An internationally acclaimed Nanoelectronics researcher, he has published over 500 papers and holds 50 patents, including 20 issued US patents, with 15 licensed for commercialization. His group’s joint IP with semiconductor industries is used in millions of ICs globally. Prof. Rao co-founded two successful deep technology startups, Nanosniff and Soilsens, at IIT Bombay. He has been elected Fellow of multiple prestigious academies and supervised 53 Ph.D. graduates. Prof. Rao has received over 40 awards and honors, both in India and abroad, including 3 honorary doctorates. He chairs various government of India committees on education and research matters.
Prof. Krishnendu Chakrabarty
School of Electrical, Computer and Energy Engineering, Arizona State University, USA.
Title
Where There Is a Will, There Is a Vulnerability: Threats to Multi-Tenant FPGAs and Countermeasures Based on ML-Based Detection
Abstract
FPGAs are ubiquitous in cloud computing, offering flexibility and high performance across diverse applications. Multi-tenancy is typically used to exploit the full potential of FPGAs. However, multi-tenancy introduces major security vulnerabilities. An adversary may exploit dynamic reconfigurability by deploying malicious power-wasters such as ring oscillator (RO)-based circuits on the FPGA. The ROs can cause abrupt voltage fluctuations, leading to fault-injection in a user bitstream and denial of service.
To detect the malicious power-wasters and block them from FPGA configuration, machine learning (ML)-based techniques incorporating convolutional neural networks and graph convolutional networks have been explored. ML models successfully detect a wide range of stealthy and emerging threats, without requiring dedicated hardware and time-intensive reverse engineering. This keynote presentation will describe the vulnerabilities of multi-tenant FPGAs and demonstrate the scalability and efficiency of ML-based detection models, paving the way for secure and reliable FPGA deployment in cloud services.
Speaker Biography
Dr. Krishnendu Chakrabarty received the B. Tech. degree from the Indian Institute of Technology, Kharagpur, in 1990, and the M.S.E. and Ph.D. degrees from the University of Michigan, Ann Arbor, in 1992 and 1995, respectively. He is now the Fulton Professor of Microelectronics in the School of Electrical, Computer and Energy Engineering at Arizona State University (ASU). He is also the Chief Technology Officer (CTO) of the SWAP Hub for the Department of Defense Microelectronics Commons (https://microelectronics.asu.edu/southwest-advanced-prototyping-hub/), and Director of the ASU Center for Semiconductor Microelectronics (http://acme.asu.edu) . He was a Visiting Professor at NVIDIA from May 2022 to January 2023. Before moving to ASU, he was the John Cocke Distinguished Professor and Chair of Electrical and Computer Engineering at Duke University.
Prof. Chakrabarty is a recipient of the National Science Foundation CAREER award, the Office of Naval Research Young Investigator award, the Humboldt Research Award from the Alexander von Humboldt Foundation, Germany, the IEEE Transactions on CAD Donald O. Pederson Best Paper Award (2015), the IEEE Transactions on VLSI Systems Prize Paper Award (2021), the ACM Transactions on Design Automation of Electronic Systems Best Paper Award (2017), multiple IBM Faculty Awards and HP Labs Open Innovation Research Awards, and over a dozen best paper awards at major conferences. He is also a recipient of the IEEE Computer Society Technical Achievement Award (2015), the IEEE Circuits and Systems Society Charles A. Desoer Technical Achievement Award (2017), the IEEE Circuits and Systems Society Vitold Belevitch Award (2021), the Semiconductor Research Corporation Technical Excellence Award (2018), the Semiconductor Research Corporation Aristotle Award (2022), the IEEE-HKN Asad M. Madni Outstanding Technical Achievement and Excellence Award (2021), and the IEEE Test Technology Technical Council Bob Madge Innovation Award (2018). He is a Research Ambassador of the University of Bremen (Germany) and he was a Hans Fischer Senior Fellow at the Institute for Advanced Study, Technical University of Munich, Germany during 2016-2019. He is a 2018 recipient of the Japan Society for the Promotion of Science (JSPS) Invitational Fellowship in the “Short Term S: Nobel Prize Level” category. He is a recipient of the Distinguished Alumnus Award from the Indian Institute of Technology, Kharagpur.
Prof. Chakrabarty’s current research projects include: design-for-testability of 3D integrated circuits and heterogenous integration; hardware security; AI accelerators; microfluidic biochips; AI for healthcare. He is a Fellow of ACM, IEEE, and AAAS, and a Golden Core Member of the IEEE Computer Society. He was a Distinguished Visitor of the IEEE Computer Society (2005-2007, 2010-2012), a Distinguished Lecturer of the IEEE Circuits and Systems Society (2006-2007, 2012-2013), and an ACM Distinguished Speaker (2008-2016). Prof. Chakrabarty served as the Editor-in-Chief of IEEE Design & Test of Computers during 2010-2012, ACM Journal on Emerging Technologies in Computing Systems during 2010-2015, and IEEE Transactions on VLSI Systems during 2015-2018.
Prof. Sridevan Parameswaran
School of Electrical and Computer Engineering, The University of Sydney, Australia.
Title
Approximate Arithmetic Units and Their Application in Machine Learning
Abstract
Approximation has long enabled humans to perform rapid calculations with just enough precision for effective task execution. Human senses—such as hearing and vision—are built on approximate mechanisms, which serve exceptionally well. In mathematics, approximation techniques like rounding or the Newton-Raphson method for integration are frequently relied upon. Similarly, approximation has become critical in computing, with techniques such as MP3 encoding removing unnecessary audio components to create smaller files.
This talk will focus on a hardware-driven approach to optimizing AI circuits and systems by reducing the size of integer and floating-point multipliers and dividers. Approximate arithmetic units, however, often introduce bias, where errors skew positively or negatively. This bias can accumulate across units in complex AI systems, potentially degrading performance or reliability. Therefore, minimizing bias is essential to designing practical AI circuits that support large-scale, real-time processing. A novel design method and specialized circuits will be presented, which deliver compact, highly energy-efficient, and minimally biased approximate units. These designs are particularly well-suited for AI applications, where minor approximations can significantly reduce area and energy use without impacting overall accuracy. Applications will be illustrated in which approximation has a negligible effect on output, enabling more efficient AI architectures with potentially reduced reliance on fixed-point arithmetic. This approach opens up new possibilities for building smaller, faster, and more energy-conscious AI systems.
Speaker Biography
Sri Parameswaran is a Professor and Head of School in the School of Electrical and Computer Engineering at the University of Sydney. Before joining the University of Sydney, he was a Professor and Interim Head of School at the School of Computer Science and Engineering at the University of New South Wales. He received his B.Eng. degree from Monash University and his Ph.D. from the University of Queensland in Australia.
He has held visiting appointments at the University of California, Kyushu University, and the Australian National University. His experience also includes consulting for NEC Research Laboratories in Princeton, USA, and the Asian Development Bank in the Philippines. His research interests focus on System Level Synthesis, Low Power Systems, High-Level Systems, Network on Chips, and Secure and Reliable Processor Architectures.
He served as the Editor-in-Chief of IEEE Embedded Systems Letters and has been involved with the editorial boards of IEEE Transactions on Computer-Aided Design, ACM Transactions on Embedded Computing Systems, the EURASIP Journal on Embedded Systems, and the Design Automation of Embedded Systems. He has participated in program committees for conferences such as the Design Automation Conference (DAC), Design and Test in Europe (DATE), the International Conference on Computer-Aided Design (ICCAD), the International Conference on Hardware/Software Codesign and System Synthesis (CODES-ISSS), and the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES). He is a Fellow of the IEEE.